• Electrical Engineering Archive: Questions from 2023-02-16

    For a pseudo-NMOS inverter fabricated in a 0.13-um process and having kn = 5kp = 500 uA/V2, Vtn = -Vtp = 0.4 V, and VDD = 1.3 V, find VOH , VOL, and Isat. Hence, find the static power dissipation in the low-output state.
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    Design a pseudo-NMOS inverter that has equal capacitive charging and discharging currents at vO = VDD/4 for use in a system with VDD = 2.5 V, |Vt| = 0.5 V, k
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    Use Eq. (15.26) to find the value of r for which NML is maximized. What is the corresponding value of NML for the case VDD = 1.3 V and Vt = 0.4 V? Show that NML does not change very much with r by evaluating NML for r = 2, 5, and 10.
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    For what value of r does NMH of a pseudo-NMOS inverter become zero? Prepare a table of NMH and NML versus r, for r = 2 to 10. Let VDD = 1.3 V and Vt = 0.4 V. Use your table and iteration to determine the value of r that results in NML = NMH. What is the resulting margin?
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    Design a pseudo-NMOS inverter that has VOL = 0.1 V. Let VDD = 1.8 V, |Vt| = 0.5 V, k
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