It is required to design a minimum-area pseudo-NMOS inverter with equal high and low noise margins using a 1.3-V supply and devices for which |Vt| = 0.4 V, k
This problem investigates the effect of velocity saturation (Section 15.1.3) on the operation of a pseudo-NMOS inverter fabricated in a 0.13-um CMOS process for which VDD = 1.3 V, Vt = 0.4 V, kn = 5kp = 500 uA/V2, and |VDSsatp| = 0.6 V. Consider the case with vI = VDD and vO = VOL. Note that QP will be operating in the velocity-saturation region. Find its current IDsat and use it to determine VOL.
A Pseudo NMOS inverter shown in Figure below operates with drain current ID = 100 uA and supply voltage VDD = 3.3 V. Calculate (W/L) ratio of load transistor. Assume K'N = 100 uA/V2, K'p = 40 uA/V2, VTN = 0.60 V, VTP = -0.60 V.
Calculate (W/L) ratio of switching transistor. A Pseudo NMOS inverter shown in Figure below operates with drain current ID = 100 uA and supply voltage VDD = 3.3 V. Calculate (W/L) ratio of switching transistor. Assume K
The following circuit uses a CMOS pass-transistor logic (PTL) gate. Assume Vpp = 5V and that the transistor parameters are: unCox(W/L) = 200 uA/V2, upCox(W/L) = 100 uA/V2, IV_t] = 1.2V (for both nmos and pmos transistors) and v = 0 (neglect body effect). a) Find IDN,1, the current through the NMOS transistor if VA = 0 V and the capacitor is charged so that vc is 90% of VDD. b) Find IDP,1, the current through the PMOS transistor if VA = 0 V and the capacitor is charged so that vc is 90% of VDD. c) Find IDN, 2, the current through the NMOS transistor if VA = 0 V and the capacitor is charged so that vc is 10% of VDD. d) Find IDP,2, the current through the PMOS transistor if VA = 0 V and the capacitor is charged so that vc is 10% of VDD. e) Use the average-current method to estimate the fall time, tf, defined as the time needed for vc to go from 90% to 10% of VDD.