Assume the total capacitance on the output is 24fF, a 35.1nA leakage current discharges the output towards ground, and that the gate is clocked at 2MHz. What will be the final output voltage in volts for a dynamic 4-input NOR gate if all the NMOS FETs have a logic "0" on their inputs. Use: VDD = 3.3V, VTN = 0.7V, VTP = -0.7V, k'n = 100uA/V^2, k'p = 40uA/V^2
What will be the final output voltage in volts for a dynamic 4-input NOR gate if all the NMOS FETs have a logic "0" on their inputs. Assume the total capacitance on the output is 22fF, a 32.8nA leakage current discharges the output towards ground, and that the gate is clocked at 3MHz. Use: VDD = 3.3V, VTN = 0.7V, VTP = -0.7V, k'n = 100uA/V^2, k'p = 40uA/V^2
What will be the final output voltage in volts for a dynamic 3-input NAND gate if the top NMOS FET has a logic "1" on it's input and the bottom 2 NMOS FETs have a logic "0" on their inputs. Assume the total capacitance on the output is 39fF, and there is 14fF on each of the nodes between the series NMOS FETs. Neglect leakage. Use: VDD = 2.5V, VTN = 0.4V, VTP = -0.6V, kn = 150uA/V^2, k'p = 60uA/V^2
What will be the final output voltage in volts for a dynamic 4-input NAND gate if the top 3 NMOS FETs have a logic "1" on their inputs and the bottom NMOS FET has a logic "0" on it's input. Assume the total capacitance on the output is 89fF, and there is 6fF on each of the nodes between the series NMOS FETs. Neglect leakage. Use: VDD = 2.5V, VTN = 0.4V, VTP = -0.6V, k'n = 150uA/V^2, k'p = 60uA/V^2