A dynamic 2-input NAND gate is shown below. The charge sharing between CL and Ca happens when B = 0, and A = 0->1. If VDD = 2 V, and the change in the output is Vout = 1 V, calculate the ratio of the capacitances Ca/CL.
For the given domino logic circuit in Figure 2, during evaluation if A=1, B=0, C=0 and D=0, will cause charge sharing and the input to the inverter will drop. The minimum voltage required at the inverter input is 3V. What should be the maximum CP/CL ratio to avoid charge sharing affect the correct output at F?
During the evaluate phase, VA = VB = 2 V, and VC = 0 V. Use the charge sharing method, compute the final voltages at the Vout and 20 fF and 8 fF capacitors. Assume that VT = 0.7V.
For the given domino logic circuit in Figure 3, during evaluation, if A=1, B=1, C=1 and D=0 will cause charge sharing and the input to the inverter will drop. The minimum voltage required at the inverter input is 3V. What should be the maximum CP/CL ratio to avoid charge sharing affect the correct output at F?
For the given domino logic circuit in Figure 1, during evaluation, if A=1, B=1, C=0 and D=0, will cause charge sharing and the input to the inverter will drop. The minimum voltage required at the inverter input is 3V. What should be the maximum CP/CL ratio to avoid charge sharing affect the correct output at F?
Charge Redistribution/Charge Sharing: If Vdd = 1.5 V, CA and CB have initial zero charges. After the charge redistribution, what is the Vout? CA/CL = 1/5, CB/CL= 1/3
Consider the following Domino's Dynamic Logic. Node X is connected to a CMOS inverter so that the output of the inverter can be directly fed to the next stage of the Domino's circuit. Assume that node X is pre-charged to VDD = 5 volts. Of course charge sharing will take place between CX and CY, depending on the input to the logic. Assume that CX is =CY and that the initial voltage across CY is 0. Assume that the inputs to the logic are 1 (input to M1) and 0 (input to M2) a) What is the function of this logic? Find an expression of the final voltage at node X (i.e. after the charge sharing) b) What should the ratio of Kp/Kn of the inverter be to prevent any logic error (due to charge sharing between nodes X and Y) under any circumstances? Assume that Vtn = -Vtp = 1 volt
Charge sharing is an important problem in dynamic circuits. Switching exposes a fixed amount of charge to a different capacitive environment. This results in node voltage change. After pre-charge stage, the output node voltage of the dynamic logic circuit in Figure 1 will be equal to VDD. During the evaluate phase, assume A = 1 and B=0. Output node will not connect to ground but the total charge on the output node (Q = C.V) will be shared by parasitic capacitance (C1) and the load capacitance (CL). So that the output voltage will drop and be equal to M1 source voltage. a. The circuit is Figure 1 is pre-charged with VDD = 3V. During evaluation stage, M1 turns on and M2 is off (A=1 and B=0). CL = 250fF, C1 = 125fF and Vt0,n=0.55V. Calculate the final voltage after charge sharing. Is M1 still conducting at this voltage? b. Repeat question a for C1 = 40fF. Calculate the final voltage after charge sharing. Is M1 still conducting at this voltage? If not, what is the value of the output voltage at this scenario? c. With A = 1 and B = 0, the output of the circuit in Fig 1 should be logic high. However, you have seen that logic high does not mean VDD for this example. Output voltage depends on the parasitic capacitance at the source node of M2. For a dynamic 2 input NAND gate, what is the maximum value that the Figure 1 output voltage can reach when A= 1 and B = 0?