(a) Calculate the voltage at which vO = vI for a CMOS inverter with Kn = Kp. (Hint: Always remember that iDN = iDP.) Use VDD = 2.5 V, VTN = 0.6 V, VTP = -0.6 V. (b) What is the current IDD from the power supply for vO = VI if (W/L)N = 2/1? (c) Repeat the calculation in (a) for a CMOS inverter with Kn = 2.5Kp. (d) What is the current IDD from the power supply for vO = VI if (W/L)N = 2/1?
(a) Repeat Prob. 7.10 for VDD = 3.3 V, VT N = 0.75 V, and VT P = -0.75 V. (b) Repeat Prob. 7.10 for VDD = 2.5 V, VTN = 0.60 V, and VTP = -0.50 V.
What is the switching threshold (where does vI = vO) for a minimum size inverter in which both W/L ratios are 2/1 if VDD = 2.5 V and VTN = -VTP = 0.6 V?
What is the switching threshold (where does vI = vO) for a minimum size inverter in which both W/L ratios are 2/1 if VDD = 1.8 V and VTN = -VTP = 0.45 V?
What are the noise margins for a symmetrical CMOS inverter operating with VDD = 3.3 V and VT N = -VTP = 0.75 V? (b) Repeat for a CMOS inverter having (W/L)N = (W/L)P operating with VDD = 3.3 V and VTN = -VTP = 0.75 V.
The outputs of two CMOS inverters are accidentally tied together, as shown in Fig. P7.22. What is the voltage at the common output node if the NMOS and PMOS transistors have W/L ratios of 20/1 and 40/1, respectively? What is the current in the circuit?
(a) For the CMOS inverter in Figure 16.21 in the text, let VDD = 3.3 V, VTN =+0.4 V, and VTP = -0.4 V. Assume (W/L)n = 4 and (W/L)p = 12. Determine (i) the input switching voltage, (ii) the input voltage when vO = 3.1 V, and (iii) the input voltage when vO = 0.2 V. (b) Repeat part (a) for (W/L)n = 6 and (W/L)p = 4.