Consider the CMOS dynamic logic circuit shown in Figure 2, which is a simple domino circuit. Node X is connected to a CMOS inverter so that the output of the inverter can be directly fed to the next stage of the domino circuit. Problem 2.1 Explain how the voltage level at node X, after it is precharged to 5V, can be affected by the charge sharing between node X and node Y if their node capacitances are the same. Express the final voltage at node X in terms of the initial voltage at node Y when the charge sharing is completed, following the full precharge operation when input B is fixed at 0V. Problem 2.2 Determine the ratio between device transconductance parameters, kp and kn, of the inverter to prevent any logic error due to charge sharing between nodes X and Y under all circumstances. Assume that the magnitudes of the threshold voltages in the inverter are equal to 1.0V.
Consider the CMOS dynamic logic circuit shown in Figure 4, which is a simple domino circuit. Node X is connected to a CMOS inverter so that the output of the inverter can be directly fed to the next stage of the domino circuit. Problem 2.1 Explain how the voltage level at node X, after it is precharged to 3V, can be affected by the charge sharing between node X and node Y if their node capacitances are the same. Express the final voltage at node X in terms of the initial voltage at node Y when the charge sharing is completed, following the full precharge operation when input B is fixed at 0V. Assume CX=CY. Problem 2.2 Determine the ratio between device transconductance parameters, kp and kn, of the inverter to prevent any logic error due to charge sharing between nodes X and Y under all circumstances. Assume that the magnitudes of the threshold voltages in the inverter are equal to 1.0V. Assume CX=CY.
Consider the CMOS logic circuit shown in Fig. P9.7, which is a simple domino circuit. Node X is connected to a CMOS inverter so that the output of the inverter can be directly fed to the next stage of the domino circuit. a. Explain how the voltage level at node X, after it is precharged to 1.2 V, can be affected by the charge sharing between node X and node Y if their node capacitances are the same. Express the final voltage at node X in terms of the initial voltage at node Y when the charge sharing is completed, following the full precharge operation when the gate terminal of transistor M2 is fixed at 0 V. b. Determine the ratio between device transconductance parameters, kp and kn, of the inverter to prevent any logic error due to charge sharing between nodes X and Y under all circumstances. Assume that the magnitudes of threshold voltages in the inverter are equal to 0.45 V. The use of Level 1 transistor current equations is deemed adequate.
Consider the CMOS logic circuit, which is a simple domino circuit. Node X is connected to a CMOS inverter so that the output of the inverter can be directly fed to the next stage of the domino circuit. a. Explain how the voltage level at node X, after it is precharged to 5 V, can be affected by the charge sharing between node X and node Y if their node capacitances are the same. Express the final voltage at node X in terms of the initial voltage at node Y when the charge sharing is completed, following the full precharge operation when the gate terminal of transistor M2 is fixed at 0 V. b. Determine the ratio between device transconductance parameters, kp and kn, of the inverter to prevent any logic error due to charge sharing between nodes X and Y under all circumstances. Assume that the magnitudes of threshold voltages in the inverter are equal to 0.45 V. The use of Level 1 transistor current equations is deemed adequate.
Given the following circuit, assuming that all inputs of the circuit shown in Figure 1 below are initially 0 during the precharge phase and that all internal nodes are at 0V: a. Calculate the voltage drop on V0, if A changes to 1 (VDD = 2.5 V) during the evaluate phase. It is given that Vtn = 0.5 V, 2φF = 0.6 V and γ = 0.4 V0.5 . Hint: Don’t forget the body effect. b. Now calculate the voltage drop on Vo if both A and B change to 1 (under the above conditions). c. What is the maximum number of transistors that can be connected in series to M1 and M2 (including M1 and M2, excluding M0 ) if the output should not fall below 0.9 V during the evaluate phase? Assume that each one of the new transistors has the same intrinsic capacitance (to ground) as M1 and M2 (C=10fF).
Consider the domino circuit in Fig.3. Assuming that all inputs of the circuit shown in Fig.3 are initially Low (0V) during the pre-charge phase and that all internal nodes are at 0V. Ignore all other parasitic capacitance except C1, C2, and C3. It is given that VDD=2.5V, Vtn0=0.5V, 2phif=0.6V and gamma=0.4V^0.5. (25pts) (a) Calculate the voltage drop on Vout (OUT node voltage) if A changes to High (2.5V) during the evaluation phase. (10pts) (Hint: Don't forget the body effect.) (b) Calculate the voltage drop on Vout (OUT node voltage) if both A and B change to High (VDD=2.5V) (5pts). (c) What is the maximum number of transistors that can be connected in series to M1 and M2 (including M1 and M2, excluding M3) if the output should not fall below 0.9V during the evaluation phase? Assume that each one of the new transistors has the same intrinsic capacitance (to ground) as M1 and M2 (C=5fF). (10pts)
Consider the circuit as shown below, assume that all inputs are 0 during the pre-charge phase and all the internal nodes are initially 0 V. Suppose all the nMOS transistors have the same Vtn0 = 0.6 V, 2phiF = 0.5 V, and gamma = 0.35V1/2. With CA = 60fF,CB = 10fF, CC = 10fF, calculate the voltage drop on Vo if: (a) Only B changes to 1 (VDD = 3.0 V) during the evaluation phase. Do not ignore body effect (i.e., don't assume Vsb = 0 V ). (b) Both A and B changes to 1 (VDD=3.0 V) during the evaluation phase. Ignore body effect here (Vsb = 0V) (c) Only A changes to 1 (VDD=3.0 V) during the evaluation phase. Do not ignore body effect.
Consider the circuit as shown below, assume that all inputs are 0 during the pre-charge phase and all the internal nodes are initially 0V. Suppose all the nMOS transistors have the same Vtn0 = 0.4V. Ignore the body effect and calculate the voltage drop on Vo, if: (a) Only A changes to 1 (VDD=2.5) during the evaluate phase. (b) Both A and B change to 1 (VDD=2.5V) during the evaluate phase. (c) Only A, and C change to 1 (VDD=2.0V) during the evaluate phase.
The inputs to a domino logic gate are always LO during the precharge phase ( phi = LO) and may undergo a LO-to-HI transition during the evaluation phase ( phi = HI). Consider the domino 3-input AND gate shown in Fig. P9.6 below. If, during the evaluation phase, A = HI, B = LO, and C = LO, charge sharing will cause the voltage at the input of the inverter to drop. Given that the switching threshold of the inverter is 3 V, calculate the maximum ratio CP/CL necessary to ensure that charge sharing does not corrupt the value of F for the given case.