7.26. In the circuit of Fig. 7.62, (W/L)1 = 10/0.18 and ID1 = 0.5 mA. a. If λ = 0, determine (W/L)2 such that M1 operates at the edge of saturation. b. Now calculate the voltage gain. c. Explain why this choice of (W/L)2 yields the maximum gain. 7.27. The CS stage of Fig.7.62 must achieve a voltage gain of 5 . a. If (W/L)2 = 2/0.18, compute the required value of (W/L)1. b. What is the maximum allowable bias current if M1 must operate in saturation?
Design this Cascode amplifier with ideal current source load. Q1 and Q2 should be identical NMOS transistors. The negative output voltage swing should be as close to zero as possible, what is the value you achieve? All transistors must remain in saturation, of course. unCox = 350 uA/V2 Vtn = 0.50 V gm1 = 2 ma/V Rout = 200 kohm VAn = 7.5 Lmin = 0.18um Lmin < L < 3.5Lmin VOV = 0.25 V Find a) Avo b) ro c) W L d) VG2 e) I f) Voutmin ?
A MOSFET amplifier is shown below. Assume unCOX(W/L) = 2mA/V2 , Vt = 2 V, and λ = 0. Assume also that the capacitor has zero impedance at the frequency of the source signal. a) Circle which type of a single stage amplifier is represented by Q1. Explain why. Q1: Common-source Common-gate Common-drain b) Draw the small-signal circuit, and find the small-signal gain, vout/vsig, input resistance, RIN, and output resistance, ROUT.
Improve the output resistance of a pmos current load (transistor) with a cascode transistor. If designed for Vov = 0.2 V for both transistors, the maximum high output voltage (close to VDD) is maintained. upCox = 70 uA/V2 Vtp = -0.80 V gm1 = 1 ma/V Rout = 200 kohm IOUT = 100 uA VDD = 3.3 V Find a) W/L ratios b) VG3 ? c) VG4 ? d) The maximum output voltage
Figure 3 shows a current source. The NMOS transistor parameters are VTN = 0.4 V, kn = 100 uA/V2, lambdan = 0 and the PMOS transistor parameters are VTP = -0.6 V, kp = 40 uA/V2, lambdap = 0. The width-to-length ratios are (W/L)1 = 15, (W/L)2 = (W/L)3 = 9, and (W/L)4 = 20. Assume IREF = 200 uA. What is the value of I0.