The following figure shows a pseudo-NMOS inverter gate, in which gate-grounded PMOS acts like resistive load. Assume VDD = 2.0V, unCox = 100 uA/V2, upCox = 50 uA/V2, VTHN = 0.4V, VTHP = -0.4V, lambda_n = 0, and lambda_p = 0. When (W/L)n =10 and Vin = VDD, Vout = 0.2V. Determine (W/L)p. Also assume that both NMOS and PMOS operate in linear region although PMOS actually operates in saturation region.
For a pseudo-NMOS inverter implemented in a 0.4um technology (i.e. 0.4um is the minimum dimension of transistor gate). with kn' = 3kp' = 300 uA/V2, VDD = 2.5V and VTN = -VTP = 0.5V. (a) Complete the following table. Each row contains the integer value of r (r = kn/kp) and the corresponding NML and NMH values. (b) Based on the r value shown in the first column, if the W/L of the NMOS in this inverter is set to (0.6 um/0.4 um), what are the W/L, Width and Length of the PMOS, respectively? Note that PMOS chip area (WxL) should be minimized. Calculate the associated static power consumption for NMOS and PMOS, respectively, and for each value of r in the table whenever the inverter output is a logic 0,
For a pseudo-NMOS inverter implemented in a 0.25um technology (i.e. 0.25um is the minimum dimension of transistor gate). with kn' = 3kp' = 360 uA/V2, VDD = 2.5V and VTN = -VTP = 0.6V. (a) Complete the following table. Each row contains the integer value of r (r = kn/kp) and the corresponding VIL and VIH values. (b) Based on the r value shown in the first column, if the W/L of the NMOS in this inverter is set to (0.6 um/0.4 um), what are the W/L, Width and Length of the PMOS, respectively? Note that PMOS chip area (WxL) should be minimized. Calculate the associated static power consumption for NMOS and PMOS, respectively, and for each value of r in the table whenever the inverter output is a logic 0,