Consider a pseudo-NMOS inverter fabricated in 0.35-um CMOS technology for which assuming lambda1 = lambda2 = 0, Vtn = -Vtp = Vt, kn = 300 uA/V2, Vt = 0.3 V, VDD = 2 V, and kn = 3kp. (a) Find VOH and VOL. (b) Evaluate the values of VOH and VOL and find the average power dissipated in the inverter, assuming it spends half the time in each of its two states.
Consider a pseudo-NMOS inverter as shown in Fig. 16.21 and fabricated in a 65-nm CMOS technology for which VDD = 1.0 V, IVt| = 0.35 V, kn/kp = 5.4, and kn = 540 uA/V2. (a) Find VOH. (b) Derive an equation for VOL that is a function of VDD, Vt, and kn/kp. (c) Evaluate the equation using the process parameters in the problem statement.
Problem 4.1 Sizing. Figure 1 shows a circuit known as a pseudo-NMOS inverter since the depletion-mode NMOS device has been replaced with a grounded-gate PMOS. Using the following device parameters for the transistors: NMOS: VT0 = 0.6V, L = 1.0 um, lambda = 0.0V-1, unCox = 60 uA/V2 PMOS: VT0 = -0.6V, L = 1.0 um, lambda = 0.0V-1, upCox = 20 uA/V2 and assuming the power supply voltage VDD is 3.3 V, find the (Wn/Wp) ratio so that the switching (inversion) threshold voltage of the circuit is VM = 1.4 V. Problem 4.2 Vin Overdrive. Calculate the required input voltage Vin to force the output voltage to be 0.7V for the circuit you designed in Problem 4.1.
The circuit at right is known as a "pseudo-NMOS" inverter. (Note that is very similar to CMOS except that the PMOS gate voltage is fixed at -VDD) In the circuit, the NMOS has VTN = 1 V and KN = 0.5 mA/V2. The PMOS has VTP = -1 V and Kp = 0.1 mA/V2. Calculate the output voltage and total power being dissipated in the circuit for Vi, = 0.5 V, 2.5 V, and 5 V.