Consider the two transistor circuit on the right. Vdd = 2 V, kn = 200 uA/V^2, kp = 100 uA/V^2 and Vtn = |Vtp| =0. 5 V. Find a value for Vin such that Vout = 1 V.
It is required to bias the MOSFET amplifier shown in Fig. 1 below at point Q for which VOV,Q = 0.2 V and VDS,Q = 1 V. It is required to bias the MOS amplifier of Fig. 7.3 at point Q for which VOV = 0.2 V and VDS = 1 V. Find the required value of RD when VDD = 5 V, Vt = 0.5 V, and kn = 10 mA/V2. Also specify the coordinates of the VTC end point B. What is the small signal voltage gain of this amplifier? Assuming linear operation, what is the maximum allowable negative signal swing at the output? What is the corresponding positive peak input signal?
Consider an NMOS transistor fabricated in a 0.18 - um process with L = 0.18 um and W = 2 um. The process technology is specified to have Cox = 8.6 fF/um^2, un = 450 cm^2/V?s, and Vtn = 0.5 V. a) Find VGS and VDS that result in the MOSFET operating at the edge of saturation with ID = 100 uA. b) If VGS is kept constant, find VDS that results in ID = 50 uA. c) To investigate the use of the MOSFET as a linear amplifier, let it be operating in saturation with VDS = 0.3 V. Find the change in iD resulting from vGS changing from 0.7 V by +0.01 V and by -0.01 V.