Electrical Engineering Archive: Questions from 2023-07-18

The circuit shown below shows a PMOS transistor operating as a switch in the ON position. (a) If initially vO= 0 and at t = 0, vI is raised to VDD, what is the final value VoH reached at the output? (b) If initially vO = VDD and at t = 0, vI is lowered to 0 V, what is the final value VOL reached at the output? (c) For the situation in (a), find tPLH for vO to rise from 0 to VDD/2. Let kp = 225 uA/V^2, VDD = 1.8 V, and |Vtp| = 0.5 V and C = 10 pF.

The figure shows a MOSFET biased with a constant current source. The parameters are VTP = -0.8V, conduction parameter Kn = 0.12 mA/V2. Calculate the values of Source to Gate voltage, VSG AND Source to Drain voltage, VSD. Choose TWO of the answers given below corresponding to these voltages. Incorrect answers OR selecting anything greater than 2 choices will result in a grade penalty.

Using the process data parameters for long-channel (1 um) length MOSFET, estimate the delay through the circuit shown below. Ensure you estimate both tPHL and tPHL. What are the maximum and minimum output voltages across the capacitor? Can the output of the NMOS charge all the way to VDD, if you wait long enough?

The PMOS cascode circuit below must provide a bias current of 0.5 mA with an output impedance of 40 kΩ. If μpCox = 50 μA/V2 and λ = 0.2 V −1 , determine the required value of (W/L)1 = (W/L)2.

What is the voltage at point A in the circuits shown below? What happens in (g) if the PMOS is removed? Does the circuit work better or worse? Why? Note that in all of these circuits the p-substrate (body of the NMOS) is grounded and the n-well (body of the PMOS) is at VDD.

The MOS cascode of Fig. 9.47 must provide a bias current of 0.5 mA with an output impedance of at least 50 kohm. If unCox = 100 uA/V^2 and W/L = 20/0.18 for both transistors, compute the maximum tolerable value of lambda.