Do the sizing of the following circuit Y=(AB+CD+EF) with respect to the reference inverter sizing (PMOS-2 and NMOS-1). Find the worst-case rise time and worst-case fall time for the same.
Size the transistors in the following circuit such that the worst-case pull-up and pull down drive strengths are the some as an inverter with PMOS width of 2 and NMOS width of 1 . Size of transistor A is given for both PUN and PDN.
Size the transistors in the following NFET network. Timing constraint: t <= RnCL. un/up = 2. Rn is the resistance of a 1X NFET. Try to minimize the total TR width heuristically.
Problem 2: The sizing of the NMOS and PMOS transistors is shown in the inverter to have similar tpHL and tpLH. A complex gate structure is shown toward the right to produce the logic function F=D+A.(B+C) (a) Find the logical values of the inputs that generate the longest tpHL. (Points: 5) (b) Find the logical values of the inputs that generate the longest tpLH. (Points: 5) (c) Find the sizing of all the transistors to have the same propagation delays of the given inverter. (Points: 20)
Design a circuit for a static CMOS logic cell which is realized by Z=A.(B+C)+D.E. Size the devices so that the worst-case drive resistance is the same as an inverter with WN/L=1 and WP/L =2.
Consider the static CMOS gate shown below. Assuming that un/up=1.5 and Vthn= |Vthp|. As consequence, a reference, balanced inverter for this technology has an NMOS width Wn=1 unit and a PMOS width Wp=1.5 units. What Boolean function does this gate implement?
3(a) A CMOS circuit is shown in Figure 4. Size the transistors in the circuit for more or less symmetrical delay under worst case conditions. Minimize the size as much as possible. Assume un = 2up. Show the size of each transistor in the diagram. Use a minimum transistor size of 10/2. (Note: Certain paths wont happen.) b) Redesign the circuit to minimize the number of transistors (you may use either pass logic or gate logic design).
10.34 (Transistor Sizing): Find appropriate sizes for transistors used in the XOR circuit in the text (see figure below). Assume that the basic inverter has (W/L)n= 0.75um/0.5um and (W/L)p=3.0um/0.5um (i.e. no =1.25,po=6 ). What is the total area, including that of the required inverters? FIGURE 10.15 Realization of the exclusive-OR (XOR) function: (a) The PUN synthesized directly from the expression in Eq. (10.25). (b) The complete XOR realization utilizing the PUN in (a) and a PDN that is synthesized directly from the expression in Eq. (10.26). Note that two inverters (not shown) are needed to generate the complemented variables. Also note that in this XOR realization, the PDN and the PUN are not dual networks; however, a realization based on dual networks is possible (see Problem 10.27).
The following (in the next page) shows an NFET network of Y in Problem 4. Size the transistors so that the fall delay is less than or equal to RnCL where Rn is the resistance of a IX NFET. Minimize the total width. Find the total width.
A nMOS and a pMOS are implemented in the circuit shown below. A, B, and C are set at 0, 6.212, and 1.473 volts (with respect to the GND). What is the potential of D ? Assume that R is large and conduction thresholds are +-2 volts.
Size the transistors in the following gate to satisfy the time constant. You should minimize the total width of the transistors. Size the transistors in the following pFET network to satisfy the time constant. Try to minimize the total width of the transistors.
b) Size the transistors in this gate so that the worst-case on resistance for the pull-up and pull-down networks are the same as that for the static CMOS inverter. c) Size the transistors in this gate so that the best-case on resistance for the pull-up and pull-down networks are the same as that for the static CMOS inverter.
The PMOS transistor network of a CMOS logic function is shown in Figure 2. All transistors used are of size 30/2. Find the size of an equivalent PMOS transistor for the input values shown.
Size the transistors in the shown logic gate, so that tPHL = 30 ps and tPLH = 106 ps. The gate is connected to external load of 80fF. All transistors have minimum length L = 2λ = 0.25 um. Use the following values for the transistor resistances: Rsq,n = 13 kΩ and Rsq,p = 31 kΩ. Neglect the capacitances at the internal nodes and assume that the external load capacitance is much greater than the transistor capacitances.
Design the PMOS transistor network. Select the device sizes for both the NMOS and PMOS transistors to give a delay of approximately one-half the delay of the CMOS reference inverter (W/L=2/1 for NMOS, W/L=5/1 for PMOS). C is the same.
Size the transistors in the circuit below so that it has the same drive strength, in the worst case, as an inverter that has PW=3 and NW=2. Use the smallest widths possible to achieve this ratio. Write down the size next to each transistor.
What is the small signal voltage gain when IQ = 5mA? The parameters of the transistors are lambda_n = 0, VTN = 1 V, kN = 400 uA/V2, beta = 99, VA = infinite and VBE(on) = 0.7 V
In the circuit of fig. 7.51, M1 and M2 serve as current sources, Calculate IX and IY if VB=1 V and W/L=20/0.25. How are the output resistances of M1 and M2 related?
Calculate the total charge stored in the channel of an NMOS transistor under the following conditions: CoX =10fF/um2, W=5um, L=0.1um, and VGS -VTH=1 V. Assume VDS =0. An NMOS transistor conducts 1 mA when VGS-VTH=0.6V and 1.6 mA when VGS - VTH =0.8 V. Calculate VDS and W/L if the transistor is operating in the triode region. Determine the operating region of M1 in each of the circuits shown in Figure 1.
Consider the following enhancement MOSFET circuit. The transistor is tested in the laboratory and following results are obtained: VGS(ON)=2V and ID(ON)=1 mA. The threshold voltage is also found to be VTH=1.5 Volts. Find ID, VGS and VDS.
A MOSFET process produces the following parameters. (a)Calculate the threshold voltage, VT. (b) What should the ion implantation be to make this an enhancement mode device intended to operate in a 3.3 V operating circuit? (c)Find n and S in the subthreshold region. (d) Find the transconductance, gm = ∂ID/∂VGS for VGS = 2.5 V, VDS = 1.0 V, L = 0.25 μm, W = 10 μm, θ = 0.12 V−1. ΦMS = −0.4eV, ϕf = 0.4 V, Cox′ = 7×10−7 F/cm2, CB′ = 2×10−7 F/cm2 QB(2ϕf) = −5×10−8 C/cm2, Qf = Qit(2ϕf) = q×1010 C/cm2
The parameters of the transistors are lambda_n = lamnda_n = 0, VTP =-2.7 V, VTN = 2.7 V, kP = 300 uAN^2, and kN = 200 uA/V^2. Determine Vout in the circuit such that vin =10sin?(wt) mV, RF = 200 kohm and VDD=6V.
When considering channel length modulation, draw an equivalent circuit and use it to obtain the voltage gain. (Assume that it operates in the saturation mode)
Consider the MOSFET diff-amp with the configuration in Fig. 4. The circuit parameters are V+ = 3V, V- = -3V, and IQ = 200μA. The transistor parameters are VTN = 0.4V, kn’ = 100μA/V2, W/L = 10, and λ = 0. The range of the common mode input voltage is to be -1.5 ≤ vcm ≤ +1.5V, and the common mode rejection ratio is to be CMRRdB = 50 dB. a) Design the diff-amp to produce the maximum possible differential-mode voltage gain. b) Calculate the maximum possible differential-mode voltage gain.
In this question assume any transistors are fabricated in 180 mm node technology. (a) You are asked to design the realisation of the following CMOS logic operation Y = A + B ⋅ (C + D + E) subject to the following performance criteria that the transistor dimensions in the pull-up (pull-down) network should be able to provide a current of at least that found in a PMOS (NMOS) transistor with a (W/L) ratio equal to p(n), respectively. (i) Sketch the arrangement of transistors using static CMOS logic which would realise Y. (ii) What is the width of each transistor in the network? Show clearly your calculations.
Find the intrinsic gain Av and output impedance Rout for the amplifier when I1 = 0.01 and 0.1 mA respectively. (Neglect body effect) Parameter for NMOS: VTHN = 0.7 V, Kn = 110 μA/V2, λ = 0.04 V-1 Parameter for PMOS: VTHP = -0.7V, Kp = 50 μA/V2, λ = 0.05V-1 All the size of transistor is W = 20 μm, L = 1 μm.
Given a MOSFET with the following characteristics: Vth = 0.8 Volts VA = 100 Volts μCoxW/L = 1.0 mA/V2 (a) Select RD, R1 and R2 to result in VDQ = 16 Volts, ID = 2 mA and IR1 = 1 mA. (b) Determine the small-signal gain
The parameters of the transistors are λn = λp = 0, VTP = -2.7 V, VTN = 2.7 V, kP = 300 μA/V2 , and kN = 200 μA/V2 Determine vout in the circuit such that vin = 10 sin(ωt) mV, RF = 200 kΩ and VDD = 6 V.
Find the intrinsic gain Av for the amplifier when ISS = 0.02 and 0.2mA respectively. (Neglect body effect) Parameter for NMOS: VTHN = 0.7 V, Kn = 110 μA V2 , λ = 0.04 V-1 Parameter for PMOS: VTHP = -0.7 V, Kp = 50 μA/V2 , λ = 0.05 V-1 All the size of transistor is W = 20 μm, L = 1 μm.
A reference inverter has (W/L)n = 1.5, (W/L) p = 10. Assuming a load capacitance is doubled, what are the new NMOS and PMOS transistor sizes to reduce the propagation delay by 70%? (Hint: propagation delay is proportional to the RC time constant of the inverter).
Calculate the value of drain current in the circuit below. (W = 5 μm, L = 0.5 μm and λ = 0) In the following problems, unless otherwise stated, assume μnCox = 200 μA/V2, μpCox = 100 μA/V2 , and VTH = 0.4 V for NMOS devices and -0.4 V for PMOS devices.
Using the following small signal model for NMOS, please calculate gain A = vout/vin in terms gm, C1, C2, RD, RL, RS and RG. (alpha numeric study) Draw the bode plot for gain and phase vs frequency diagram.
Figure 1 shows a network of logic gates driving a load capacitance CL. The value of CL is 20+ the final two digits of your URN. (i) Find the normalised delay D. Show clearly your calculations. (ii) Select the sizes of gates x and y to minimise the delay from A to B along the path indicated.
We wish to design the circuit shown in figure for a voltage gain of 0.8 with a power budget of 3 mW. Compute the required value of W/L. Assume C1 is very large and λ = 0. Circuit parameters μnCox = 200 μA/V2, VDD = 1.8 V, VTH = 0.4 V, RL = 60 Ω.
For the circuit shown below, If μnCox = 200 μA/V2, VTh = 0.4 V, λ = 0.1 V−1 and W L = 20/0.18 , the small-signal transconductance is
A CMOS inverter circuit is shown below. In which regions are the transistors operating, in region 2 of the transfer curve? a. NMOS Active, PMOS Passive b. NMOS Triode, PMOS Saturation, c. NMOS Cut-off, PMOS Triode, d. NMOS Saturation, PMOS Cut-off, e. NMOS Saturation, PMOS Triode
Find the intrinsic gain Av for the amplifier when ISS = 0.02 and 0.2mA respectively. (Neglect body effect) Parameter for NMOS: VTHN = 0.7 V, Kn = 110 μA/V2, λ = 0.04 V-1 Parameter for PMOS: VTHP = -0.7 V, Kp = 50 μA/V2 , λ = 0.05 V-1 All the size of transistor is W = 20 μm, L = 1 μm
Find the intrinsic gain Av and output impedance Rout for the amplifier when I1 = 0.01 and 0.1 mA respectively. (Neglect body effect) Parameter for NMOS: VTHN = 0.7 V, Kn = 110 μA/V2, λ = 0.04 V-1 Parameter for PMOS: VTHP = -0.7 V, Kp = 50 μA/V2, λ = 0.05 V-1 All the size of transistor is W = 20 μm, L = 1 μm
Calculate the voltage gain, input impedance and output impedance of given amplifier circuit. Gm1 = 3mS, gm2 = 1mS, rd1 = rd2 = 10 K, R1 = 2 K, R2 = 1 K V1 and V2 are the dc bias voltages Vi is the triangular waveform with a peak voltage of 0.5V.
Draw an equivalent circuit considering the channel length and use it to obtain the voltage gain (The current source is ideal. Assume that all Transistors operate in the saturation mode)
A. Consider the common source amplifier given in Fig. 4. i. Assume KN = 0.43 mA/V2, VTN = 1.2 V, and = 0.001 V-1. Determine the values of the R1 and RD resistances if VDD = 12 V, IDQ = 1 mA, VDSQ = 6 V, R2 = 10 kΩ ii. Determine the small signal gain AV with RL = 10 kΩ.
In the circuit below, NMOS is VTH = 0.5 V, μnCox = 10-4 A/V2, W/L = 6/0.2 In the circuit below, PMOS is VTH = -0.5 V, μnCox = 10-4 A/V2, W/L = 6/0.2 Both NMOS and PMOS are λ = 0.1, which means the degree of channel length modulation effect. Vin is 0.005*sin(2000t)[V]. (1) Draw a small signal circuit to find the magnitude of the amplitude of the output signal for the circuit below. (2) Find the magnitude of the amplitude of the output signal for the circuit below.
Design the circuit of figure below, so that the transistor operates in Saturation with Id = 0.5 mA and Vd = +3 V Let the NMOS transistor have Vt = 1 V and kn’(W/L) = 1.5 mA/V2 assume x = 0. What is the largest value that RD can have while maintaining Saturation region operation? Calculate Vgs and Vs for the parameter value given.
Estimate the maximum low frequency voltage gain for the amplifier shown at 27∘C with Rd = 39.3 kΩ, Rs = 3.6 kΩ.
For the circuit shown below, assume the following MOSFET parameters: Kn = 200 µA/V^2, Vt = 2 V, lambda = 0. If the following resistor values are used: R1 = 3 Mohms, R2 = 1Mohm, Rd = 4.7 kohms, Rs = 2.7 kohms, RL = 10 kohms, Cc1 = 0.01 uF, Cc2 = 1uF, and Cs = 100 uF, determine the midband voltage gain of the amplifier (ignoring loading factors due to source or load resistances).
Assume λ = 0 and all devices are in saturation region. 1. Identify Feedback Type of the circuit ( V-V / V-I / I-V / I-I) 2. Construct (draw) open-loop circuit using feedback analysis 3. Compute the closed loop gain using feedback analysis 4. Compute the closed-loop I/O impedances using feedback analysis.
The transistor parameters: VTP = -1 V, kp = 2 mA/V2, λ = 0 and by using Table2. a) Find VSGQ and VSDQ of the FET amplifier as shown in Figure 2. b) Derive an expression for mid-band voltage gain (vo/vs) of the FET amplifier. c) Sketch the gain (vo/vs ) in dB versus frequency. Clearly label all break points. Note 1: When designing the circuit, please show the solution step by step. Note 2: The values of all results must be four digits after the point.
D 8.42 The circuit in Fig. 8.15(a) is fabricated in the 0.18-μm CMOS process whose parameters are specified in Table K.1 (Appendix K). VDD = 1.8 V. Design the circuit to obtain a voltage gain Av = -20 V/V. Use devices of equal length L operating at I = 100 μA and |Vov| = 0.2 V. Determine the required values of VG, L, (W/L)1, and (W/L)2.
For the following figure please determine the sizes of 2nd and 3rd stage inverters to that the delay is minimized. What is this minimum delay value in terms of the internal delay of first inverter? (Please assume γ = 1). Can you reduce this delay by adding inverters after the 3rd stage?
For the MOSFET bias circuit shown, what value of Rd in kilohms is needed to allow the maximum possible peak-to-peak signal swing on the drain without clipping? Use: Vdd = 10V, Rg1 = 51.6kΩ, Rg2 = 58.2kΩ, Rs = 9.7kΩ, Vt = 0.5V, and Von = 0.46. (Remember that Von = Vov = Vgs - Vt) Neglect the effect of channel-length modulation and body effect. (Hint: Be sure to keep the MOSFET in saturation!)
The NMOS amplifier shown has VDD = 15 V, RS = 500 Ω, RL = 10 kΩ, RSR = 3 kΩ, RD = 5 kΩ, RG1 = 700 kΩ, RG2 = 300 kΩ, VM = -150 V, Vt = 2.4 V, and Kn = 2.042 mA/V2. Calculate (a) the input resistance Rin = vs/is, (b) the no-load voltage gain Av = vo/vg, (c) the output resistance Ro, and (d) the overall voltage gain Av = vL/vS .
In the circuit of Fig. 5.8, (W/L)N = 10/0.5, (W/(L)P = 10/0.5, and IREF = 100 μA. The input CM level applied to the gates of M1 and M2 is equal to 1.3 V. (a) Assuming λ = 0, calculate VP and the drain voltage of the PMOS diode-connected transistors. (b) Now take channel-length modulation into account to determine IT and the drain current of the PMOS diode-connected transistors more accurately.
The parameters of the transistor in the circuit shown below are Vth = 0.9 V, kn = 1/2kn’(W/L) = 0.85 mA/V2 , and λ = 0.01V-1 . Determine the small-signal voltage gain of the amplifier circuit when ID = 0.1 mA, RD = 6.43 kΩ, and RS = 38.6 kΩ. Give your answer to two decimal points.
The DC analysis results for obtaining the small-signal equivalent (SSE) model parameter values of the transistor placed in the circuit given in Figure 1 are gm = 4mA/V and ro -> ∞ (open circuit). The resistor values are given as follows: R1 = 40kΩ, R2 = 40kΩ, RSi = 10kΩ, RD = 100kΩ and RS = 1kΩ. a) Draw the AC model of the whole circuit in Fig. 1 by replacing the transistor with its SSE model. State the type of the transistor and circuit topology. (Drawing the AC model of the circuit at the last step is sufficient, showing the steps of drawing is not wanted.) b) Rin =? RO = ? Avo =? Av =? Gv = ?c) If vin = 10mV, then find vO = ?