For VDD as 1.8 V, Fig. 2 shows the common-drain amplifier (source follower). Vin is a 10-KHz sinusoidal signal with amplitude equal to 0.5mV(Vp-p = 1mV). (a) Please show VG, VBIAS, and (W/L)1,2 that you design to make the voltage gain higher than 0.9 V/V and output DC level between 0.76 and 0.84 V in LTspice. Note that voltage gain is the ratio of output amplitude to input amplitude. (We assume using 0.18 um technology in this design. Thus, width and length of NMOS must be not smaller than 0.25 and 0.18 um respectively.) (b) Please check both M1 and M2 operating in the "saturation region," and display it in separate waveforms (VDS > VGS - VTH). (c) Please use small signal model to calculate its small signal gain. (You must take ro into consideration)