This is an incomplete complex CMOS logic gate in which only the NMOS transistors of the pull-down network (PDN) are displayed, but not the pull-up network (PUN) transistors. a) Write the logic function for the output (Y) based on the shown PDN configuration. b) Use De Morgan's laws to rearrange the logic function from expression from part (a) to obtain an expression which the configuration of PMOS transistors in the PUN can be designed directly. c) Draw the corresponding schematic of the PUN.
Design a Cascode current mirror and generate the same values of I1, I2, and I3 starting from a reference SINK of 2uA value For the circuit shown below, If Iref = 1 uA, then Is Iref considered a source or a sink reference current? Circle the right answer Is I3 a source or a sink reference current? Circle the right answer
Q3. [LTSPICE] Design and build a Cascode current mirror as shown below. [3 points]. Use 1.8 V for VDD a. At VX1, do DC sweep from 0 V to 1.8V while setting VX2 and VX3 at 1.5V. b. At VX2, do DC sweep from OV to 1.8V while setting VX1 and VX3 at 1.5V c. AtVX3 do DC sweep from OV 10 1.8V while setting VX1 and VX2 at 1.5V
The circuit of Fig. 12.60 samples the input on C1 when CK is high and connects CI and C2 when CK is low. Assume (W/L)1 = (W/L)2 and C1 = C2. (a) If the initial voltages across CI and C2 are zero and Vin = 2 V, plot Vout versus time for many clock cycles. Neglect charge injection and clock feedthrough. (b) What is the maximum error in Vout due to charge injection and clock feedthrough of M1 and M2? Assume the channel charge of M2 splits equally between C1 and C2. (c) Determine the sampled kT/C noise at the output after M2 turns off.
13.20. The circuit of Fig. 13.63 samples the input on C1 when CK is high and connects C1 and C2 when CK is low. Assume that (W/L)1 = (W/L)2 and C1 = C2. 13.21. If the initial voltages across C1 and C2 are zero and Vin = 2 V, plot Vout versus time for many clock cycles. Neglect charge injection and clock feedthrough. 13.22. What is the maximum error in Vout due to charge injection and clock feedthrough of M1 and M2? Assume that the channel charge of M2 splits equally between C1 and C2. 13.23. Determine the sampled kT/C noise at the output after M2 turns off.