The diagram below shows the structure of an inverter circuit built using an NMOS transistor of size 3/2, and a pull up resistor RD = 1kohm. Assuming zero body-bias, find the region of operation of the transistor and iD for a. vI = VDD/2 (2 points ) b. vI = VDD/3 (2 points) Repeat the above question with RD = 100kohm. ( 3 points) Note: 2lambda = 0.18 um is a convention used to represent transistor dimensions in terms of the technology length lambda. This is different from channel length modulation parameter. Sizing is shown in the form of W/L and as a factor of transistor feature size i.e. 2lambda. Assume long-channel device.
A set of I-V characteristics for an nMOS transistor at room temperature is shown in the table below for different biasing conditions. The figure shows the measurement setup. Using die table and the below parameters: W/L = 2 tox = 18 A |2phiF|= 1.1 V a) Calculate the threshold voltage (VT0) b) Electron mobility (un) c) Body effect coefficient gamma (y).
The width and length of the transistor have been fixed. Assume ro >> RD. (a) Fig. 1 (1) Assuming that you are designing a low-power common-source amplifier, should you bias the transistor at a large overdrive voltage or a small overdrive voltage? And why? (2) Assuming that you are designing a high-speed common-source amplifier, should you bias the transistor at a large overdrive voltage or a small overdrive voltage? And why? (3) Assuming that you are designing a high-gain common-source amplifier, should you bias the transistor at a large overdrive voltage or a small overdrive voltage? And why? (4) Assuming the subthreshold slope factor n for MOSFET is 1.5, calculate gm assuming the transistor is in deep subthreshold and consumes 1 uA of current. Thermal voltage = 25 mV.
Sketch Vo versus Vi for the circuits as Vi varies from 0 to VDD. Identify important transition points. Channel-length modulation and the body effect can be ignored. (1) Mark the different operation regions of M1 and M2 in the plot. Please note that we assume MI is always in the saturation region in Fig. 5a. (2) Provide symbolic expressions for Vi and Vo at important transition points.
Compute the gate and subthreshold leakage currents of the 3 -input NOR gate shown below for each input state: Use the following assumptions: Use "Floating" for any intermediate voltage between 0 and VDD; Threshold voltage is Vtn for NMOS and |Vtp| for PMOS. PMOS gate leakage is negligible (0); NMOS gate leakage at: Vgs=VDD is 5nA. Vgs =0 is 0 Total subthreshold leakage is the summation of all OFF PMOS or NMOS leakage currents; NMOS subthreshold leakage at Vgs=0: Vds=VDD is 4nA; Vds=0 is 0. PMOS subthreshold leakage at Vgs=0: Vsd =VDD is 8nA. 0
For the inverter pictured below, suppose that the threshold voltage is decreased from 0.4 V to 0.2 V, what is the new subthreshold leakage current as a factor of the original subthreshold leakage current? Note: You can assume the thermal voltage kT/q ~ 25mV. Note that the Schockley model is not sufficient here. VDD=1.2V. Bp = Bn = 25 uA/V2 n = 1.5 (Subthreshold slope factor) Threshold voltages: VTN=|VTP|=0.4 V about 200x about 2x about 0.5x 1x (unchanged)
The subthreshold leakage current in an NMOS transistor is given by the following expression: iD = ISe^VGS/nVT. The constant value IS in this expression is proportional to e-Vt/nVT (Do not confuse Vt with VT, Vt is the threshold voltage value and V, is the thermal voltage value). Assume n = 2, if the threshold voltage of an NMOS transistor is reduced by 0.1V, by what factor the static power dissipation increase?
The current Is in the subthreshold conduction Eq. iD = Ise^vGS/nVT is proportional to exp(-Vt/nVT). If the threshold voltage of an NMOS transistor is reduced by 0.1 V, by what factor will the static power dissipation increase? Assume n = 2. Repeat for a reduction in Vt by 0.2 V. What do you conclude about the selection of a value of Vt in process design?
The current IS in the subthreshold conduction Eq. (15.13) is proportional to e-Vt/nVT. If the threshold voltage of an NMOS transistor is reduced by 0.1 V, by what factor will the static power dissipation increase? Assume n = 2. Repeat for a reduction in Vt by 0.2 V. What do you conclude about the selection of a value of Vt in process design?
Measurements on a MOSFET operating in the sub-threshold conduction region indicate that the current changes by a factor of 10 for every 80-mV change in vGS and that iD = 20 nA at vGS = 0.16 V. (a) Find the value of iD at vGS = 0. (b) For a chip having 1 billion transistors, find the current drawn from the 1-V supply VDD as a result of subthreshold conduction. Hence, estimate the resulting static power dissipation.
An nMOS transistor has a threshold voltage of 0.4 V and a supply voltage of VDD = 1.2 V. A circuit designer is evaluating a proposal to reduce VDD by 100 mV to obtain faster transistors. a) By what factor would the saturation current increase (at Vgs = Vds = VDD) if the transistor were ideal? b) By what factor would the subthreshold leakage current increase at room temperature at Vgs = 0? Assume n = 1.4. c) By what factor would the subthreshold leakage current increase at 120 deg C? Assume the threshold voltage is independent of temperature.