Electrical Engineering Archive: Questions from 2023-09-16

Question 1( d): In the following circuits, find range of Vin in which transistors remain in saturation. Kn = 200 uA/V2, Vth = 0.5 V, Vdd = 2 V, W/L = 10

Sketch IX as a function of VX, where VX varies from 0 to 3V. Assume VTH = 0.7 V, gamma = 0 and lambda = 0. Indicate the boundary voltage between the linear and the saturation region. Assume IX =0 for VDS < 0 V.

Given that the layout in (a) is a minimum sized inverter with minimum size nmos and pmos devices, identify the logic function and draw the equivalent transistor level schematics for each of the following layouts labelled (b) and (c). Include transistor sizes, inputs/outputs, Vdd, and Gnd labels. Hint: You should need a ruler to complete this question.

The parameters of the pMOS and nMOS transistors are given below: pMOS Vtp = -0.5 V Vtn = 0.5 V μpCox = 200 μA/V2 (W/L)p = 5 nMOS μnCox = 500 μA/V2 (W/L)n = 2 VDD = 1.5 V (a) Calculate the rise and fall time of the transmission gate in Figure 2.