Let us consider a NAND logic gate. This circuit implements the boolean function (A.B). The . stands for the AND operation, and the - stands for NOT; combining them, we get NAND! Figure 1: NAND gate transistor-level implementation. Vtn and Vtp are the threshold voltages for the NMOS and PMOS transistors, respectively. Assume that VDD > Vtn, |Vtp| > 0. (a) Label the gate, source, and drain nodes for the NMOS and PMOS transistors (please redraw the circuit). (b) If VA = VDD and VB = VDD, which transistors act like open switches? Which transistors act like closed switches? What is Vout? (c) If VA = 0V and VB = VDD, what is Vout? (d) If VA = VDD and VB = 0V, what is Vout? (e) If VA = 0V and VB = 0V, what is Vout? (f) Write out the truth table for this circuit.
Consider a digital system of a million (10^6) CMOS gates that flip state every 10^3 cycles on average. Assume that Vdd = 1.5 V and gate capacitance = 250 pF. a) Determine the total dynamic power consumed by the circuit when operated at at a clock rate of 1GHz. b) Repeat part a) assuming a frequency of 500 MHz and no change in the operating voltage. c) Repeat part b) assuming that due to the lower frequency the voltage has been sealed down to 0.75 V.
(a) Calculate the rise and fall time of the transmission gate in Figure 2. (b) How can you make the rise and fall time of the transmission gate identical? 3. The parameters of the pMOS and nMOS transistors are given below: pMOS Vtp = -0.5 V Vtn = 0.5 V μpCox = 200 μA/V2 (W/L)p = 5 nMOS μnCox = 500 μA/V2 (W/L)n = 2 VDD = 1.5 V