For an NMOS differential pair, It VDD = VSS =2.5 V, kn'W/L = 3 mA/V2, Vtn = 0.7 V, I = 0.2 mA, RD = 5kohm, and neglect channel-length modulation. Let vG2 = 0 and vG1 = vid. Find the value of vid that corresponds to each of the following situations: a) iD1 = iD2 = 0.1 mA b) iD1 = 0.15 mA and iD2 = 0.05 mA c) iD1 = 0.2 mA and iD2 = 0 mA d) iD1 = 0.05 mA and iD2 = 0.15 mA e) iD1 = 0 mA and iD2 = 0.2 mA For each case, find vS, vD1, vD2, and (vD2 - vD1).
Draw the CMOS transistor schematic for OAI22. Find width for the transistors such that it has roughly equal rise and fall times and has a worst-case pull-down resistance approximately equal to the effective channel resistance of a unit nMOS. b) Consider the Boolean equation for your gate. Find a set of inputs b, c, and d such that y = a(bar).
For the shown PMOS amplifier driving load RL with the following parameters: Vdd = 2.5v RL = 10 kohm Vt = -0.5v lambda = 0.67 v-1 W/L = 10 upCox = 50.0 uA/v2 IBias = 100 uA a) Find the value of VIN for VOUT equal to zero. Hint: Current through the load resistor, RL, is zero b) Write a small signal model for this amplifier in SPICE. Hint: Don't need Vin , and know VIN when VOUT = 0 (part a) which helps calculate gm and g0 (r0 = 1/g0) c) Simulate your model and study the results, can you measure the gain for th given load (RL) ? d) Find its small signal gain Av = VOUT/VIN. Hint: Easy to find as you already have g0, gm, and RL e) Find the range for VOUT that the PMOS stays in the saturation region. f) Find the range for VIN that the PMOS stays in the saturation region. Hint for d and e: VOUT = (-ID-IBias)?RL
Diff-Amp: The PMOS transistors within the diff-amp in Fig 2 are designed to have gm = 1.5 mA/V at 120 uA. The drain resistors are designed at 12 kohm. Finally, the current mirror of 1( b) is used as the tail current. a. Calculate the differential-mode gain of the circuit. b. Calculate the common-mode gain of the circuit. c. Calculate the minimum Vdd that this circuit can support for an input common-mode voltage of 1.8 V, including body effects. Fig. 2
The equation to determine cutoff is VGS > Vtp. What is this inequality in terms of vG ? What range of gate voltage of these transistors will result in cutoff? b) (10 pts) The equation to determine cutoff is VGS > Vtp. What is this inequality in terms of vs? What range of source voltage of these transistors will result in cutoff? c) 10 (pts) The equation to determine saturation is VDS < VGS - Vtp. What is this inequality in terms of vD ? What range of drain voltage of these transistors will result in saturation? d) (10 pts) The equation to determine saturation is VDS < VGS - Vtp. What is this inequality in terms of vG? What range of gate voltage of these transistors will result in saturation? Use the TSMC 0.18 um process parameters below. For any other parameters, use the transistor parameters in the tsmc018.mod.txt file. Use the TSMC 0.18 parameters above. Consider the PMOS transistor. In this problem, 1 decimal place in your answers is sufficient.
Calculate the tpLH and tpHL of a CMOS inverter that is driving a 50fF load (ignore all intrinsic capacitances). Assume (W/L) of the nMOS device is 1 and the (W/L) of the pMOS device is 2. Also assume the following parameter values: VDD = 2 V, VTn = 0.7 V, VTp = 0.7 V, un = 560 cm2/VS, up = 220 cm2/VS, ESi = 3.5
The Figure below shows a Wilson current source. Given all the MOSFETs have the following parameters: Vtn = 2 V, kn
The figure below shows a circuit that consists of two BJTs. Both transistors Q1 and Q2 are constructed with similar geometry and design parameters. The supply voltage, Vcc = 7 V, and the value of the resistor, R, is 6.3 kohm. Assume all the transistors are biased in the active region with similar current gain, B = 100, and base-emitter voltage, VBE = 0.7 V. (a) State the type of the circuit shown above. [3 marks] (b) State one disadvantage of using BJT compared to MOSFET in this application. [3 marks] (c) Determine the collector current of transistor Q2. [5 marks] (d) Determine the collector current of transistor Q1. [4 marks] (e) Explain the cause of the mismatch between the input reference current, IR, and the output current, IC1. [5 marks] (f) Suggest a circuit topology that reduces the mismatch between the input reference current and the output current. Sketch and label the suggested circuit. Use only BJTs in your proposed circuit. [5 marks]
Design Case: The I-V characteristics of a NMOS device is to be studied. Especially, the relationships between IDS, VGS, and VDS are to be found. Find the I-V characteristics of a NMOS with size W/L = 2u/0.4u by performing the following simulations: 1. Run a DC simulation and demonstrate IDS curve when VGS is swept from 0 V to 2 V. > Set VDS=1 V. > Plot the VGS VS. IDS curve. > Q1.1: What is the threshold voltage (VTH) of the given transistor? Q1.2: Explain how gm can be calculated from the VGS Vs. IDS curve. 2. Run a DC simulation and show IDS curve when VDS is swept from 0V to 2 V. > Set VGS = 700mV. > Plot VDS VS. IDS Curve. > Q2.1: At what VDS does the transistor transit from linear region to saturation region? > Q2.2: Does the given device suffer from channel length modulation effect? Q Q2.3: If it suffers from channel length modulation, how can it be fixed? Q2.4: Explain how ro can be calculated from the VDS vs. IDS curve. * For all design sessions, use nfet33 for NMOS and pfet33 for PMOS from "cmrf8sf" library.
W/L ratio that results in Veff = 200mV at ID = 0.5 mA, ignoring channel-length modulation (CLM) b. If this device is used in a common-source amplifier (Fig 1(a)), what is the maximum achievable gain, independent of drain resistance? c. Find the gain for the circuit when using the maximum value of drain resistor which still results in the circuit remaining in saturation. d. If M1 is replaced with a PMOS cascode (biased at 0.5 mA and both devices sized according to 1(a)), with the lower (cascode) device biased at 2 V gate voltage, what is the maximum achievable gain, independent of drain resistance? e. Find the gain for the circuit when using the maximum value of drain resistor which still results in all transistors remaining in saturation. f. Discuss what fundamentally limits the gain of these circuits. Fig 1 For the questions below, assume the following device parameters: Kn
Consider a CMOS inverter with minimum gate lengths, Wn = 15, Wp = 35 , and equivalent capacitance at the output node of 80fF. Calculate tPLH and tpHL using the following methods. The numerical answers are shown. You need to show the equation, the equation with values substituted for the variables and the final value calculated. a) (5 pts) average current method (tPLH = 23.6 ps) b) (5 pts) velocity saturation approximation (tPLH = 47.3ps) Use the TSMC 0.18 um process parameters below. For any other parameters, use the transistor parameters in the tsmc018.mod.txt file.
1. Derive the expression to compute the switching threshold of a CMOS inverter. 2. Find the static current in a unit CMOS inverter with n=1.5 and T=300 K: a. Input = 0 b. Input = 1 3. Impact of threshold voltage: repeat question 2 with a forward body-bias (FBB) of 0.11 V for both the transistors in the inverter VDD = 1.8 V unCox = 160 uA/V2 upCox = 80 uA/V2 VDSATn = 0.35 V |VDSATp|= 0.6 V Lmin = 2 Wmin = 4 Vth0n = |Vth0p| =0.4 V 2lambda = 0.18 um. Note: 2lambda = 0.18 um is a convention used to represent transistor dimensions in terms of the technology length lambda. This is different from channel length modulation parameter. Sizing is considered a factor of transistor feature size i.e. 2lambda. Unit CMOS inverter: Wn = 4lambda, Wp = 8lambda. Assume long-channel device.