Figure P5-1 shows a common source single transistor MOSFET amplifier utilizing an N-Channel Enhancement Mode MOSFET. The term "common source" refers to the source terminal being shared by both the input circuit and the output circuit. The parameters for the MOSFET and the supply voltage are also given. Hand Analysis P1. In terms of DC bias, determine a value for VGS to set the drain current ID to 5 mA. Also determine a value for RD to set the VDS bias to 6 V. P2. In terms of small-signal parameters, determine the transconductance gm of this amplifier as well as the voltage gain, Av. P3. If vgs is a 0.1 Vpk sinewave at a frequency of 1 kHz [ie. vgs = 0.1sin(2pift)V ] determine an expression for the output voltage vOUT as a function of time. Sketch vIN and vOUT for two complete cycles, including the DC bias for each signal. Simulation P4. Simulate the circuit of Figure P5-1 to verify your hand analysis and create a plot similar to P3 as part of your prelab. Use the virtual MOSFET model in simulation with SPICE parameters VT0 = 1.8 V and KP = 120 mA/V2. (The default values of 100um for W and L will be fine since their ratio equals unity.)
A MOSFET amplifier can be simplified as the equivalent circuit model shown below (very similar to the BJT version), where gm (transconductance) and RL (load resistor) can be designed to have the desired gain of the amplifier. (a) Determine the voltage gain of this MOS amplifier (Vout /Vin )?(10/10) (b) Design the load resistor RL to achieve a voltage gain ( Vout /Vin ) of 60 dB if gm = 25 mA/V.(10/100) (b) Design the transconductance gm to achieve a voltage gain (Vout /Vin ) of 40 dB if RL = 1.2 Kohm.(10/100)
Large Signal Analysis: Considered the circuit shown below, sketch vOUT as a function of vIN as vIN changes from 0 to 3 V. Assume VTH = 0.5 V. Ignore the channel length modulation effect. Label all important region changing points and the corresponding mode of operation. [Hint: MOSFET is a symmetrical device, so carefully think about which is the source and which is the drain]
The NMOS transistor in the circuit below has (1/2)kn’(W/L) = 100 mA/V2, and Vt = 1V. The PMOS transistor has (1/2)kp’(W/L) = 100 mA/V2, and Vi = -1 V. Find VD, VG, VS, and ID for each transistor.
Find the small-signal gain expression of the following circuits. Express the answer in small-signal parameters. Assuming all transistors are in the saturation region. All voltages labeled with upper-case are just DC voltages, which should not be involved in the gain expression.
The MOSFETs in the circuit below have (1/2)kn’(W/L) = (1/2)kp’(W/L) = 12 mA/V2, Vt = 1.2 V for the NMOS, and Vt = -1.3 V for the PMOS. (a) With no load connected to the output, fill in the truth table below. (b) Assume A = B = C = 5 V (all inputs high), and the output has a 3 Kohm resistive load connected as a pull up resistor from VOUT to 5 V. Find the deviation of the output voltage from its ideal value of 0 V. (c) Assume A = B = C = 0 V (all inputs low), and the output has a 3 Kohm resistive load connected as a pull down resistor from VOUT to 5 V. Find the deviation of the output voltage from its ideal value of 5 V.