For a NMOS transistor with following parameters: Vd = 3.5v Vs = 1.5v Vt = 1.0v W = 1600 nm L = 200 nm unCox = unEox/tox = 40.0 uA/v2 a. If the gate voltage is raised gradually from 0v to 5v, what regions of operation does the device pass through, and where are the transitions points? b. Find Ids when Vg = 3.3v?
Consider the circuit shown below. Suppose that all NMOS transistors are identical and all PMOS transistors are identical. Equivalent resistor for an NMOS transistor: RN = 8kohm Equivalent resistor for a PMOS transistor: RP = 24kohm Suppose that each circuit node (including outputs) has a capacitance value of 1pF. a) Derive a Boolean expression for the output F in terms of the inputs A and B. b) Calculate the worst-case and the best-case propagation delays, tPLH and tPHL values (total of 4 values).
2-input CMOS NAND and NOR gates have been designed with Rn = 1kohm, Rp = 2kohm, Cout = 8fF, and Cx = 2fF, where Cx is the node capacitance between the series transistors. a) Calculate the worst-case rise and fall times for this NAND gate. b) Calculate the best-case rise time for this NAND gate. c) Calculate the worst-case rise time for a 2-input CMOS NOR gate.
a) Draw the schematic for the circuit that implements F = x.(y + z + w) b) Using an inverter with Bn = Bp, as a sizing reference, determine the size of each transistor in this circuit that will equalize the nMOS and pMOS resistances. That is, specify size of each transistor (in terms of B) relative to Bn or Bp. c) If, rather than scaling transistor sizes as in part (b), we leave them all at Bn or p, identify the signal path (through which transistors) that will produce the slowest response (rise and fall).
You are tasked with designing the capacitively coupled MOSFET amplifier circuit in Figure 4. The internal capacitances of the MOSFET are negligible. Assume that the frequency of the input signal is sufficiently large such that; the coupling capacitors behave as short circuits to the signal component. The MOSFET has threshold voltage Vt = 1 V and transconductance parameter kn = 2 A/V2. i) If the DC voltage at the drain is required to be 5 V. Determine the range of DC voltages at the gate, that will keep the MOSFET in saturation mode? ii) Determine suitable values for RG1, RG2 and RD in order to keep the DC voltage of the gate at 3.5 V. You may use the following equation for the drain current of a MOSFET in saturation region. iD = kn/2(vGS - Vt)2 iii) Determine the range of input signal voltages vi, that could keep the MOSFET in saturation region for the values of RG1,RG2 and RD determined in question 2) b) ii).