Given the BJT circuit below with Vdd = 3v and RL = 20K and R1 = 1ohm. The BJT collector current is given by Ic = 1e−15∗exp(40∗Vbe) Write the equation for the DC sweep. Choose an operating point and solve for V1q= What is the AC gain at the operating point, Gain =
Given that VTND = VTNL = 1 V, KnD = KnL = 1 mA/V2, λD = λL = 0. a) Calculate VGG when VDSL = 4 V. b) Show that both transistors are operating in saturation mode. c) Calculate the voltage gain Av = Vo/VS You may need following information: iD = Kn(vGS−VTN)2 in saturation. iD = Kn[2(vGS-VTN)vDS−vDS2] in nonsaturation. vDs(sat) = vGS-VTN r0 = 1/(λIDQ) Figure 4.6 Expanded small signal equivalent circuit, including output resistance, gm = 2KnIDQ = 2Kn(VGSQ-VTN) for NMOS transistor
Figure 1 shows a single stage common source MOSFET amplifier circuit. We wish to design the circuit to meet the following design specifications: Load Resistance: RL = 100 KΩ Input Resistance: Ri > 200 KΩ Mid-band Gain: Gv = Vo/Vi = −50 ± 20% Supply Voltage: +15 Volts Circuit Capacitors: CG = 10μF; CS = 47μF; CD = 10μF Figure 1. Common Source MOSFET Amplifier Pre-lab: (a) Design the amplifier to meet the specifications above by choosing values for resistors R1, R2, RD and RS. Begin your design by choosing an appropriate value for the bias current ID. If ID ≈ 0.3 mA, assume VT ≈ 1.7 V, Kn ≈ 0.02 A/V2 and VA = 100 V(λ = 0.01 V−1). Find the small signal approximation of the input resistance Rin where Rin = R1∥R2 Find the small signal approximation of the output resistance Ro, where Ro is given as Ro = RD∥RL∥ro. The small signal mid-band gain of the amplifier is given by Gv = −gmRo where gm = 2knID = kn(VGS−VT) Once you choose ID the DC biasing of the transistor can be found using simple rules of thumb. The voltage VG should be approximately equal to VDD/3 > VT. For maximum symmetry, VD should be biased at the midpoint between VD(Max) and VD(Min). Clearly, the maximum VD is VDD and the minimum VD > VG−Vt. For example, if Vt = 1.7 V and VG = 1/3VDD = 5 V, then VD ≈ 9 V for maximum symmetry.
Calculate the capacitance in femtofarads on the output node of a 2-input NOR gate without an external load in a 0.35µm CMOS process. Assume NO diffusions are shared. Use: Wp = 9.6µm, Wn = 5.3µm, Lp = Ln = 0.35µm, Loverlap = 0.1µm, all diffusion lengths= 1.0µm, COX = 5fF/µm^2, Cjn = 0.9fF/µm^2, Cjp = 1.0fF/µm^2, Cjswn = 0.2fF/µm, Cjswp = 0.3fF/µm
Assume that CS/D = 0.5C0 fF/μm, Cgate = C0 fF/μm, RN = R0 kΩ−μm, VDD = 1 V. All numbers in the figure are in microns. a. Assume no sharing of source/drain (S/D) of a transistor. Find the propagation delay expressed in the given variables and width W that minimizes the delay of the gate from input A's rising edge to output B's falling edge. Consider the internal capacitance of the gate. b. If sharing of S/D capacitance is applied, with a fingered layout that uses a W=2 finger width, does the optimum W from (a) increase or decrease (circle one answer)? What are the capacitances of nodes B and N at this new optimal?
Use the Elmore delay approximation to find the worst-case rise and fall delays at the output for the following circuit. The gate sizes of the transistors are given in the figure. Use the assumption that the diffusion capacitance is equal to the gate capacitance, and that a minimum sized transistor has gate and diffusion capacitance equal to C. The resistance of an nMOS transistor with unit width is R and the resistance of a pMOS transistor with width 2 is also R. Also assume NO sharing of diffusion regions. (Hint: off-path capacitances can contribute to delay.)