The circuit in Figure 1 is an NMOS switch circuit. Assume VDD = 5 V, γ = 0.4 V1/2, 2∣φf∣ = 0.6 V, VTO = 1 V, kn′ = 100 μA/V2, (W/L) = 10, and λ = 0.1 V−1. The channel length modulation is applicable only in the saturation region. a. Determine the charging current to CL right after the rising edge of the input. Assume that the capacitor is completely discharge at the beginning of the transition. Make sure that you include all applicable device parameters in your calculations. b. Determine the charging current to CL when the output voltage is at 50% of VDD. Again, make sure that you include all applicable device parameters in your calculation. c. Use the results from parts a and b to estimate the low-to-high propagation delay (tpLH) of the NMOS switch in Figure 1. d. Use PSPICE and measure the tpLH of the circuit in Figure 1 and compare your results with part c. (Hint: the .model for this device is shown below of this page)
Let VDD = 5 V and IB = 1 mA. Set up the circuit in LTSpice. Calculate the required value of the resistance at the drain of M6. Use the ALD1101 and ALD1102 transistors. For the LTSpice simulation to be accurate, it will be necessary to use the correct SPICE models for the transistors. 1. Run a DC sweep simulation, sweeping the DC input common mode voltage at the input terminals, Vip and Vin. . Find the DC bias voltage at which the current through each branch of the differential pair is equal to half of IB. 2. Now, set the DC common mode voltage at the terminals to the bias voltage found in part 1. Apply a small sine wave at Vip , keeping the DC offset voltage at both terminals. A 10mV amplitude at 1kHz sine wave would be appropriate. Report the differential gain of the amplifier. 3. Apply a small sine wave to both input terminals to find the common mode gain. 4. Calculate the Common-Mode Rejection Ratio (CMRR) of the amplifier.
Find the function F realized by the CMOS Circuit. Design a simplified CMOS circuit for F with minimum number of transistors. (The circuit uses two inverters also.)
For the differential amplifier of next figure, find: a) The value of current I1, for a voltage gain of vout/vid = 80 V/V (1p) b) The vout range assuming that the input voltages at Q1 and Q2 gates are at 0V (0.5p) c) The maximum amplitude for the input signal for which the voltage gain is kept at 80 V/V. (0.5p) d) The frequency bandwidth of the amplifier if Cload = 1pF. If needed, consider all the parasitic capacitances associated with the transistors equal to 1fF. (0.5p) Data: ∣VT∣ = 1V; μCoxW/L = 800 μA/V2; λn,p = 0.05 V−1; Vdd = 5 V, Vss = −5 V
In the circuit below, the capacitor is initially discharged. VDD = 1 V, VTH = 0.2 V, β = 0.2mA/V2, and C = 1mF. For the clock voltage shown, plot the voltage waveform vC(t) for t ≥ 0, and label its steady state values.
Please design the differential amplifier shown in Fig. P3 to meet the following specifications: (1) Two NMOS transistors are matched: μnCox = 400 μA/V2, Vtn = 0.8 V, λn = 0.02 V−1, Wn = 4⋅Wp, L = 0.2μm. Please short the BODY to the SOURCE. (2) Two PMOS transistors are matched: μpCox = 200 μA/V2, Vtp = −0.8 V, λp = 0.04 V−1, Wp = TBD, L = 0.2 μm. Please short the BODY to the SOURCE. (3) ISS = 2 mA. (4) VS ≈ 0.3 V (5) The DC voltages of both vOP and vON ≈ 3.5 V. (6) The small-signal gain Av=(vop − von)/(vip − vin) ≈ 10. (7) The differential AC sinusoidal signal, vi = (vip−vin), has 100mV amplitude and 1kHz frequency. (8) VDD = 5 V. Design procedure: (a) Design Wp, Wn(= 4⋅Wp), VB, and RD by hand-calculations. Please round the resolution of Wp and Wn to 0.1μm. (Hint: λn and λp could be zero for your hand-calculations.) (b) Verify your design by a .OP simulation. Please report DC voltages of vS, vG, vOP and vON. (c) Verify your design by a .TRAN simulation. Please find Av and attach the waveforms of vIP, vIN, vOP, and vON in the same plot.
Design a CMOS circuit to perform this function: Z = (AB+C)D+E VTO,n = 0.7 V μnC0x = 75 μA/V2 VT0,p = −0.7 VμpCox = 25 μA/V2 Cload = 100fF, VDD = 3.3 V, minimum W and minimum L = 0.3μm. All nMOS transistors are identical, kn,A = kn,B = … = kn and All pMOS transistors are identical, kp,A = kp,8 =… = kp a. Draw the circuit. b. Draw graphs of PUN and PDN. c. Size the transistors such that the inverter equivalent of the circuit is symmetrical. d. Size the transistors such that tpHL < 200ps and tpLH < 200p for all cases.
Design a symmetrical CMOS inverter. Use the following parameters. VTO,n = 0.5V μnCox = 98 μA/V2 (W/L)=? VTO,p = −0.48 V μpCox = 46 μA/V2 (W/L) = ? Lmin = 60 nm VDD = 1.2 V Cload = 100fF. a. Plot VTC and calculate the critical voltage points (VOH, VOL,VIH, VIL) b. Calculate the propagation delays. c. Determine the maximum frequency of a periodic square-wave with 50% duty cycle input signal so that the output voltage can still exhibit a full logic swing from 0 to 1.2 V in each cycle. d. Calculate the dynamic power dissipation at this frequency (you have found in c.).