For the circuit given in Figure 2, calculate the differential and common mode gains Ad = Vod/Vid and Acm = Vod/Vcm if the output ( vod ) is taken differentially. Also calculate the CMRR. Output resistance RSS of the current source is 200kΩ. Ignore the output resistances of the transistors (r0) and assume the gm to be 2 mA/V⋅(vp = vcm + vid /2,vn = vcm − vid /2)
In the schematic diagram below, assume the following: VDD = +3 V, VSS = −3 V. the ratio beside each transistor is the W/L ratio, all n-type devices have kn’ = 0.1 mA/V2 and Vt = 0.6 V and λ = 0.05 V−1, all p-type devices have kp′ = 0.04 mA/V2 and Vt = −0.8 V and λ = 0.04 V−1. all transistors in the saturation region. v+ = v- = 0 V for DC. (a) Find the drain current for every transistor. (b) Find the midband gain vout/(v+ − v−) (c) The 10pF is placed in the circuit to increase Cgd to create a single, dominant high frequency pole. Assuming all other capacitors have negligible effect, estimate the high frequency cutoff fH.
For the common-gate circuit in Figure P4.48, the NMOS transistor parameters are: VTN = 1 V, Kn = 3 mA/V2, and λ = 0. (a) Determine IDQ and VDSQ. (b) Calculate gm and ro. (c) Find the small-signal voltage gain Av = vo/vi.
Consider the PMOS common-gate circuit in Figure P4.49. The transistor parameters are: VTP = −1 V, Kp = 0.5 mA/V2, and λ = 0. (a) Determine RS and RD such that IDQ = 0.75 mA and VSDQ = 6 V. (b) Determine the input impedance Ri and the output impedance Ro. (c) Determine the load current io and the output voltage vo, if ii = 5 sin ωt μA.