For the following amplifier with PMOS current source load assume NMOS (W/L)1 = 50/0.5, PMOS (W/L)2 = 50/2 and ID1 = ID2 = 0.5 mA when both devices are in saturation. (Given: μnCox = 1.34×10-4 A/V2, μpCox = 3.8×10-5 A/V2, λp = 0.05, λn = 0.1, VDD = 3V). Calculate the small signal voltage gain and the maximum output voltage swing while both the devices are saturated.
Analyze the following common gate amplifier that uses a NMOS transistor with Kn = 0.5 mA/V2 and ID = 1 mA (Ignore channel length modulation effect): a) Draw the AC-equivalent circuit using the T-model. b) Find the expressions and values for Rin, Av = Vo/Vi and Gv = Vo/Vsig.
For the following matched transistors with body and channel length modulation neglected. Draw the equivalent half-circuit and find the expressions for: a) The output resistance (Rout) b) Differential gain (vout/vid) c) CMMR for the output taken as single-ended with no mismatch and include the transistor output resistance of M3 and M4 (i.e ro3 & 1o4). (hint: find Ad1 = Vout1/Vid, Acm1 = Vout1/Vcm).
For the following problem, include channel length modulation for all transistors. Ignore body effect and all capacitors. Assume all transistors are biased in saturation. Transistors M1 and M2 are matched, and M3 and M4 are matched. (a) Draw a schematic of the equivalent small-signal circuit. (b) Derive an expression for the low-frequency small-signal gain of the circuit. (c) Derive an expression for the CMRR, CMRR = Adm/Acm.
Write the Boolean function that is realized by the circuit above. Then reformulate it in AOI canonical form. Sketch the CMOS circuit that realizes the canonical function with minimum transistors. VDD = 3V, µnCox = 50 µA/V^2, µpCox = 20 µA/V^2, Vtn = 0.5V, Vtp = -0.5V, Lmin = 0.35 µm is given for the circuit in b. The circuit has an equivalent load capacitor of CL = 50 fF. Find the transistor dimensions which provide tpHL = 1ns and tpLH = 1.25ns for worst-case conditions. Calculate the threshold voltage (VTH) of the CMOS circuit for simultaneous switching using the equivalent inverter concept. The same function is realized using pseudo-NMOS logic. Calculate VOL for worst-case conditions when a minimum-dimension PMOS transistor and NMOS transistors with dimensions found in c are used. Comment on your result. Recalculate the NMOS dimensions so that VOL = 0.2V is obtained for worst-case conditions.