Let's design CMOS logistic gate F(A, B, C, D) = A+(B∙C)+D For PMOS transistors and NMOS transistors of the same size, consider a fabrication process that is four times the resistance of the PMOS transistor. Assume that all diffusion areas have no sharing. Unit inverter refers to a minimum-sized inverter that makes rise resistance (also called pullup resistance) and fall resistance (also called pulldown resistance) equal by sizing the CMOS inverter shown in the following figure with PMOS:NMOS = 4:1. (a) Draw the transistor-level schematic of CMOS logic gate F consisting of PMOS and NMOS. (b) In the worst case scenario, size the PMOS and NMOS transistors of CMOS logic gate F to have the same rise and fall resistance as unit inverter. (c) Find the logical effect gA and intrinsic delay p of CMOS logic gate F with respect to Input A.
Assume M1, M2 are ideal (λ = 0) and M3, M4 are not ideal (λ > 0) in the following circuit. All the transistors are operating in saturation region. What is the voltage gain ACM-DM, ADM and the CMRR? Assume ΔRD ≈ 0 for ADM. Make reasonable assumptions when necessary.
Assume the NMOS FET has the same k, VT, and λ as in Problem 1. Resistances RD1, RS1, RG1, and RG2 are the same values chosen in Problem 1, so that the Q-point is the same as in Problem 1. a) Find Av if RS = 0 Ω b) Find Av if RS = 250 Ω Assume the NMOS FET has the same k, VT, and λ as in Problem 1. Resistances RD1, RS1, RG1, and RG2 are the same values chosen in Problem 1, so that the Q-point is the same as in Problem 1. a) Find Av if RS = 0 Ω b) Find Av if RS = 250 Ω
a) Figure Q4 shows an inverter consisting of a passive load (RL) and an enhancement n-MOST driver (MD). With the aid of fully labelled voltage transfer characteristics, briefly describe the operation of the inverter. b) Briefly describe the disadvantages of using passive loads over active loads in earlier inverter designs. c) The inverter in Figure Q4 is to be designed (i.e. find suitable values for the channel width and channel length of MD) to generate an output voltage of 0.2 V for a logic 0 . The supply voltage, VDD is 5 V, threshold voltage, VT is 0.5 V, resistance, RL is 2 kΩ and drive constant, β0 is 1.8×10-4 A/V-2 . d) Sketch a possible layout of your design in 4c). Assume the sheet resistance, Rsheet of the passive load is 100Ω/ square, and the minimum feature size λm and maximum alignment accuracy λa, are both 0.5μm. Make sure to include the alignment error and utilise minimal area.
The schematic of a inverter using a single MOSFET transistor is shown below: The threshold voltage of the transistor Q1 is |VT| = 1 V and channel length modulation can be neglected. (a) Identify a suitable model of the transistor for analysing the above circuit and describe the model mathematically, graphically or as an equivalent circuit. Sketch the voltage-voltage transfer characteristic, Vo - Vi, for the circuit, clearly identifying the state of the transistor based on the proposed model. (b) If the transistor is saturated where Vi < VA and not saturated where Vi > VA, derive an expression for Vo|Vi=VA in terms of the relevant circuit and transistor parameters. If kn = 100 μAV-2 and R = 100 kΩ, determine Vo|Vi=VA in terms of VDD. (c) Assuming no leakage current, calculate the VOH min of the inverter. If, instead, there is a leakage current with equivalent resistance of 3 MΩ when VGS < VT, determine the adjusted VOHmin. Calculate the power lost when Vi = VT/2 in these circumstances.
Find VX for the following circuit if (i) γ = 0 (ii) γ = 0.4V1/2 . Take β = 200 μA/V2; VTo = 1V; |2ϕF| = 0.6 V. Neglect channel length modulation.
Assume: VT = 0.6 V, k = 80 mA/V2, λ = 0. a) Choose RG1 and RG2 so that VG1 = 4.0 V and RG1 + RG2 = 1.2 MΩ b) Choose RS1 so that ID1 = 1.6 mA c) Choose RD1 so that VD1 = 4.8 VDC d) Choose RS2 so that ID2 = 1.6 mA e) Assume RL, C1, and C2 → ∞ and C3 = RS = 0. Analyze to find Rin, Rout, and Av = vo/vs = dvo/dvs f) Assume RL, C1, C2, and C3 → ∞ and RS = 0. Find Av g) Now assume C1, C2, and C3 → ∞, RS = 112 kΩ, and RL = 220 Ω. Analyze and find Av. h) Assume RS = 112 kΩ and RL = 220 Ω. Choose values for C1, C2, and C3 to set the lower -3dB frequency to 40 Hz.
a) Do the two circuits in Figure 1 implement the same logic function? Provide the Boolean expression for the circuits. b) What is the appropriate transistor sizing for the logic circuit to have similar to 1X inverter delay? Fill in the empty boxes. Assume PMOS D has width of 2, and INV1X has WPMOS:WNMOS of 2:1. c) Assume the transistors have been sized to give a worst case output resistance of 12 kohm in both pull-up and pull-down networks for the worst-case input patterns. What input patterns (A-D) give the lowest output resistance when the output is low? What is the value of that resistance? d) What input patterns (A-D) give the lowest output resistance when the output is high? What is the value of that resistance? e) Neglecting parasitics and assuming a load capacitance of 100 fF, calculate the best case tpLH and tpHL.
The circuit in Figure 1 is a seif-biased current mirror/source. Assume all pMOS transistors, M1, M2, M3, and M4 are the same size, Le. (W/L)M1 = (W/L)M2 = (W/L)M3 = (W/L)M4 ha. Assume VDD = 1.8 V. Neglect the body-effect (γ = 0) and channel-length modulation effect (λ = 0) for DC bias calculations. 1. Size all the transistors for VON = 0.1 V for Iref = Iout = 25 μA. 2. Determine the value of R. 3. What is the maximum value of Vout for this circuit to work properly? 4. Determine the output resistance Rout. Assume L = 1 μm. For this part, λ is not neglected. Figure 1 Self-biased current mirror
An inverter (NOT) gate is designed with tHL = 0.25 ns and tLH = 0.5 ns. The input voltage Vin is shown in accompanying figure, and is known that the output voltage ranges from Vout = 0v to Vout = 5 v. (a) Draw a waveform for Vout (t). (b) What is the maximum switching frequency for this circuit, if 90% and 10% of VDD are used as threshold voltage levels for logic 1 and 0, respectively? Draw a waveform of the output voltage Vout at this frequency. (c) Suppose that the input is driven at twice the maximum frequency. Draw a waveform of the output voltage in this case, and explain why the gate will not operate properly.
For the CFIA, find vo/vi using the small-signal circuit. Assume ro1,2 = ∞, but consider the body effect of M2 (for M1, assume the body is tied to the source, so no body effect). Comment on how the body effect impacts the voltage gain.
Six inverters are shown below. Assume that Kn = 2Kp and that λn = λp and that the DC bias current through each inverter is equal. Qualitatively select, without using extensive calculations, which inverter(s) has/have (1) the largest AC small signal voltage gain (2) the lowest AC small signal voltage gain (3) the highest AC output resistance (4) the lowest AC output resistance. Assume all devices are in saturation.
a) Identify the basic CMOS blocks NOT, NAND and NOR in the figure. b) Draw a schematic with gate symbol for the circuit. c) Write the Boolean expression for Y = f(A, B, C,D). d) Can you simplify the expression with any techniques from Module 2?
Consider the CMOS op amp of Fig. 9.37 when fabricated in a 0.13-µm CMOS technology for which μnCox = 4µpCox = 512 µA/V2, |Vt| = 0.4 V, and VDD = VSS = 0.65 V. For a particular design, 1 = 128 µA, (W/L), = (W/L)2 = 1/2(W/L)5 = 44.4, and (W/L)3 = (W/L)4 = 11.1. (a) Find the (W/L) ratios of Q6 and Q7 so that I6 = 128 µA. (b) Find the overdrive voltage, |Vov|, at which each of Q1, Q2, and Q6 is operating. (c) Find gm for Q1, Q2, and Q6. (d) If|VA|= 3.2 V, find ro2, ro4, ro6 and ro7 (e) Find the voltage gains A1 and A2, and the overall gain A.
In the above circuit assume that every internal node has a capacitance of Cint = 50pF. Consider that the PMOS transistor in the circuit is of size (W/L)p = 6, and all the NMOS transistors are of equal size (W/L)n = 2. Here, VDD=3.0 V Rno = 20 KΩ and Rpo = 80 KΩ Rno = resistance of an NMOS transistor of size (W/L)n = 1 Rpo = resistance of a PMOS transistor of size (W/L)p = 1 CL = 100pF a. What will be the pre-charge time (tpre) for the circuit? During pre-charge time all the inputs are 0 (zero). b. What will be the low-to-high propagation delay (tpLH) of the circuit? c. What will be the high-to-low propagation delay (tpHL) of the circuit?
A MOS differential pair operated at a bias current of 0.8 mA employs transistors with W/L = 100 and μnCox = 0.2 mA/V2, using RD = 5 kΩ, and RSS = 25 kΩ. (a) Find the differential gain, the common-mode gain, and the common-mode rejection ratio (in dB) if the output is taken single-endedly and the circuit is perfectly matched. (b) Repeat (a) when the output is taken differentially. (c) Repeat (a) when the output is taken differentially but the drain resistances have a 1% mismatch. Ans. (a) 10 V/V, 0.1 V/V, 40 dB; (b) 20 V/V, 0 V/V, ∞ dB; (c) 20 V/V, 0.001 V/V, 86 dB
Sketch vOUT1 and vOUT2 for the circuit below as vIN varies from 0 to VDD. Identify the values of the input and output at the boundaries of different operating regions of the transistor (no need for deriving the exact expressions for the curve shape). We assume ideal long-channel model, no channel length modulation and no sub-threshold.
A MOS differential pair operated at a bias current I of 0.8 mA employs transistors with W/L = 100 and μnCox = 0.2 mA/V2, using RD = 5 kΩ and Rss = 25 kΩ. Ignore ro of Q1 and Q2. (a) Find the overdrive voltage Vov of Q1 and Q2. Ignore the bias current through Rss. (b) Find the gm of Q1 and Q2. (c) Find the differential gain Ad using the gm found in (b). (d) Derive an expression for vo1/vicm and vo2/vicm. (e) Suppose the load of Q2 is replaced by RD+ΔRD, find an expression for the common-mode gain which is defined as Acm = vod/Vicm. (f) Find the Acm when the drain resistances have 1% mismatch. ( (g) Find CMRR in dB for the case of (f).
Assume that we have an inverter with VDD = 1.5 V, Kn’ = 100 uA/V2, Vtn = 0.4 V, λn = 0.1 V-1, (W/L)n = 10, Kp’ = 60uA/V2, Vtp = -0.4 V, λp = 0.2 V-1 , ( W/L)p = 17 a) Calculate VOH, VOL, and VM b) Calculate g (slope of VTC). c) Estimate VIL and VIH from g found in part b. d) Sketch a rough VTC using the parameters found in parts a through c. e) Calculate NMH and NML. f) Assuming that the load capacitance is 100 fF and using the average current technique, calculate tPLH and tPHL. g) Assuming that the load capacitance is 100 fF and using the average current technique, calculate tr and tf.
A schematic of a loaded, BJT (3C2BJT1) inverter is shown below, driving a load modelled by the resistor RL. The inverter is driven by a technology where ViHmin = 2.4 V and ViLmax = 1.4 V and power is provided as VCC = 5 V. The resistance values are as follows: RC = 3 kΩ and RB = 16 kΩ and excerpts from the datasheet of the 3 C2 BJT1 are attached. Determine the maximum value of the load resistance, RL, such that the transistor operates at the edge of saturation under worst case conditions. BJT Datasheet Excerpt (3C2BJT1) On Characteristics:
For the given CMOS logic circuit, identify and describe (graphically, mathematically or using an equivalent circuit) a suitable model of each transistor type for analysis, assuming that each of the input signals A, B, C and D are equal to 0 V or VDD. Hence or otherwise, determine the states of conduction of each transistor (in terms of ON and OFF) for all combinations of the input signals A, B, C and D. Hence, deduce the logic function, F, performed by the circuit, including indicative equivalent circuit examples of how the output voltage is determined for a low and a high output (at least one example each).
Consider the inverter based amplifier to the right. Assume ID = 5 mA, λ = 0.02, Kn’ = 100 μA/V2, W1/L1 = 30, W2/L2 = 20, Rsig = 200 kΩ, RL = 800 kΩ. (a) Determine the gain of the amplifier. (b) How does the gain change if the body/substrate terminal of Q2 is tied to ground? Assume η = 0.5.
Construct transistor-level CMOS logic circuits for the following function (using the PUN and PDN networks): Z = A∙(B+C)+DE bar
Design a transistor-level CMOS logic circuit to implement the function F = (x + y ⋅ z). (w + x + z) bar using the least number of transistors. ie: simplify the function first, then find the PUN and PDN and draw them.
The figure on the right shows a transistor level circuit that implements a CMOS gate. (a) Write a truth table for the function performed by the gate. The truth table should have two inputs A and B. (b) What is the name of this function? How many transistors do you need to implement the logic? (Hint: an inverter uses at least two transistors.)
Figure 4-1 shows a CMOS logic inverter driving a capacitive load of 100pF. The input to the inverter is a clock signal Vin switching between 0 and 5 V. Several parameters for both the PMOS and NMOS devices are also given. NOTE: The process parameters for the devices are NOT equal! a) Using a simple resistor-switch model for the MOSFETS, determine the propagation delays tPLH (low-to-high output transition) and tPHL (high-to-low output transition) for this CMOS inverter. Please indicate any assumptions that apply. b) For the given input signal VIN, carefully sketch the output voltage across the capacitor as a function of time on the graph provided. NOTE: Be sure to indicate the propagation delays on the graph. c) If two PMOS devices are connected in parallel (for M1), which propagation delay will be affected and what will its new value be? M1: P-Channel Wp = 160 μm Lp = 25 μm kp’ = 100 μA/V2 |Vtp| = 1.85 V M2: N-Channel Wn = 160 μm Ln = 25 μm kn’ = 150 μA/V2 Vtn = 1.85 V
Consider the differential pair with current mirror biasing and active loads given in figure below. Assume for both nMOS and pMOS devices; |Vth| = 1 V, |VA| = 20 V. kn(W/L) = 12.5 mA/V2 for Q1, Q2, Q3 and Q4 while kn(W/L) = kp(W/L) = 25 mA/V2 for Q5, Q6, Q7 and Q8. a. Find VGS voltages of each transistor. b. Calculate differential mode gain Adm. c. Calculate common mode gain Acm. d. Determine the input common mode range of the differential pair. ID = 1/2kn,p’W/L(|VGS|-|Vth|)2 gm = ∂ID/∂VGS.
Fig. Q2a shows a current source constructed using M1 and RS . Assuming λ ≠ 0, (i) Analyse the circuit using small-signal approach to obtain the impedance looking into the drain of M1. (ii) Identify the advantage(s) and disadvantage(s) of the circuit. (iii) With the aid of schematic circuit diagram and graph, determine a circuit technique to mitigate the disadvantages of the circuit discussed above.
Refer to the reference inverter shown below. a. A reference inverter has (W/L)n = 1.5, (W/L)p = 10. Design NMOS and PMOS network to implement, Y = AB + C(D + E) b. This logic gate drives a load capacitance of 2.5C, what are the new NMOS and PMOS transistor sizes to reduce the propagation delay by 40%?
Consider an NMOS, as shown in Fig. 2, VDD = 3 V, Vtno = 0.6 V, μnCoxW/L = 40 μA/V2, γn = 0.5 V1/2 , ϕf = 0.3 V, and λn = 0.015 1/V. The initial value of V2 is 0 V, i.e., V2(t = 0) = 0 V. Find V2(t >> 0) in the following cases under DCSS condition: (a) V1 = 1 V (b) V1 = 3 V
In the Cascode stage of the figure given below, assume that (W/L)1 = 50/0.5, (W/L)2 = 10/0.5, ID1 = ID2 = 0.5 mA and RD = 1 kΩ (a) Choose Vb such that M1 is 50 mV away from the triode region. (b) Calculate the small-signal voltage gain.
For the given CMOS logic circuit, identify and describe (graphically, mathematically or using an equivalent circuit) a suitable model of each transistor type for analysis, assuming that each of the input signals A, B and C are equal to 0 V or VDD. Hence or otherwise, determine the states of conduction of each transistor (in terms of ON and OFF) for all combinations of the input signals A, B and C. Hence, deduce the logic function, F, performed by the circuit, including indicative equivalent circuit examples of how the output voltage is determined for a low and a high output (at least one example each).
An NMOS amplifier is shown in Figure 1. Transistor M1 is biased in the saturation region for an amplifier application. The circuit is biased with a resistive voltage divider consisting of R1 and R2, a source degeneration resistor RS, and a load resistor RD. The drain bias current for the design is ID = 500 μA and VDS is 1.625 V. The device parameters are: L = 0.5 μm, W = 10 μm, kn’ = 200 μA/V2, Vtn = 0.5 V, and λn = 0. analyze the frequency response of the amplifier. a) Draw a midband small signal ac equivalent circuit model for the amplifier. For midband you can assume the reactance of Cin is sufficiently low that it is a short circuit. b) Derive an expression for the midband voltage gain transfer function Vout /Vsig. The amplified output signal is taken from the drain terminal and Vout = Vd. Write your gain function in terms of variables only. c) Evaluate the midband gain and calculate a value both in V/V and dB. d) Analyze the frequency response of the input network including the capacitor Cin. Find an expression for the transfer function H1(jω) = Vg/Vsig. e) Evaluate H1(jω) = Vg/Vsig and make a Bode plot of the magnitude of H1(jω). The x-axis is ω (log scale) and the y-axis is the magnitude in dB. f) Use the LTSPICE circuit template and verify the frequency response of the amplifier circuit. Include a copy of the schematic and the frequency response plot. Use 20 points per decade and a frequency span of 0.1 Hz to 100 Hz.