Calculate the voltage gain of the circuit shown in Fig. 17.78(a) if λ = 0. Figure 17.78 (a) Example of a composite stage, (b) simplified circuit.
For an NMOS Common-Source (CS) amplifier, ID is dc biased at 1 mA and the overdrive voltage is 0.2 V. For the small-signal equivalent circuit of the CS amplifier shown in the below figure, an overall voltage gain is found to be −10 V/V without RL. What value should a resistance RL inserted in the drain lead have to reduce the overall voltage gain to −5 V/V?
An enhancement mode n-channel MOSFET has the gate (oxide) capacitance per unit cross-sectional area is 2⋅10−6 F/cm2 and the transistor's threshold voltage of VT = 0.6 V. The channel length is 20 μm ( μm = 10−6m = micrometer). If the gate and drain electric potentials are VG = VD = 2 V, and the source is grounded (Vs = 0 V), a) Calculate the VDS(SAT): b) Is this MOSFET ON or OFF? If it is ON, is this transistor in the non-saturation or saturation region and why? c) Calculate the drain current/width (ID/W) if the effective channel mobility of electrons is 550 cm2/V/s at this gate bias.
b) By investigating the circuit shown in Figure Q1a, find the relationship among the gate-source voltages of transistors M1 - M3 that guarantees M1 is in saturation. Assume that the input voltage, Vin is equal to the power supply voltage, VDD. [4 Marks] c) Figure Q1b shows a combination of NMOS and PMOS current mirror circuits. Assume all the transistors are ideal and operating in saturation mode. Develop equations that show the relationships of the drain currents for transistors M1, M2, M3, and M4. [5 Marks] d) By analysing the current mirror circuit shown in Figure Q1c, plot and explain all the necessary conditions for VX and VY as a function of VDD. Assume that the transistors M1 and M2 are identical. [6 Marks] a) With aid of diagram, develop an equation for drain current, ID, based on a NMOS transistor in saturation region. [10 Marks]