• Electrical Engineering Archive: Questions from 2023-11-9

    Problem 6: A dynamic 2-input NAND gate is shown below. The charge sharing between CL and Ca happens when B = 0, and A = 0→1. If VDD = 2 V, and the change in the output is ΔVout = −1 V and ∣ΔVout ∣ > VTn, calculate the ratio of the capacitances Ca/CL.
    1 answer

    A ratioed logic can be implemented with a resistor as a PUN shown below. Given that, VDD = 2 V, VOL = 0.2 V, and the equivalent resistance of the PDN network is RPN = 1 kΩ. Calculate the value of the load resistor RL.
    1 answer