In this problem, we design a two-stage op amp based on the topology shown in Fig. Q1. Assume a power budget of 6 mW, a required output swing of 2.5 V, and Leff = 0.5µm for all devices. a) Allocating a current of 1 mA to the output stage and roughly equal overdrive voltages to M5 and M6, determine (W/L)5 and (W/L)6. Note that the gate-source capacitance of M5 is in the signal path, whereas that of M6 is not. Thus, M6 can be quite a lot larger than M5. b) Calculate the small-signal gain of the output stage. c) With the remaining 1 mA flowing through M7, determine the aspect ratio of M3 (and M4) such that VGS3 = VGS5. This is to guarantee that if Vin = 0 and hence VX = VY, then M5 carries the expected current. d) Calculate the aspect ratios of M1 and M2 such that the overall voltage gain of the op amp is equal to 500.
Refer to the Circuit above. For the MOSFET, VT = 1 V and k = kn’W/L = 4 mA/V2. (a) Identify the value of the gate voltage vG and the drain-source current iDS. (b) Calculate the value of the drain voltage vD using the 1 kΩ resistor. (c) Analyze the circuit to find vS. Here, use the Method of Assumed State. You must validate your assumptions. [Hint: assume vS = x]
The z-domain representation of the digital control system for an elevator is shown in Figure 2. The sampling interval is T = 0.2 s. Figure 2 (a) Confirm that one of the closed-loop poles of the system in Figure 2 is located at z = 0.17, and calculate the location of the remaining poles. [5 marks] (b) Map the closed-loop poles and zeros of the given system into the s-plane, and use them to estimate (i) the percentage overshoot and (ii) the 5% settling time, Ts±5% for a unit step input. [10 marks] (c) Do you expect frequency folding effects to contribute in this case? Give 2 reasons to support your answer. [5 marks]
The transfer function of the open-loop system G(s) = 13.0634/s2 + 6.5317×104s - 6.5317×106 for a desired point of operation. Analyze the feedback system G(s) and Gc(s) are the plant and controller of the control system, respectively, as shown in Fig. 2. Fig. 2 Block diagram of the control system (a) Determine the steady-steady error and the criterion for the closed-loop system to be stable when the reference input r(t) is a unit-step without disturbance d(t) = 0 for the following controllers. i. Proportional (P) controller (Gc(s) = Kp, Kp > 0) ii. Proportional-Integral (PI) controller (Gc(s) = Kp + Ki/s, Kp, Ki > 0) iii. Proportional-Derivative (PD)controller (Gc(s) = Kp + Kd, Kp, Kd > 0) (b) Discuss whether the P, PI, and PD controllers can be utilized to eliminate the impulse and unit-step disturbance (r(t) = 0) by analyzing steady-state responses.
Assume Gc(s) = K and G(s) = 1/(s+10)(s+1)^2 in the following block diagram. (a) Draw rough sketches of the Bode magnitude and phase plots. Determine the slopes and break points on both plots. (b) Determine the range of K for which the closed-loop system is stable by using the Bode plots obtained in part (a).
Consider a unity feedback system with forward (open-loop) Transfer Function, G(s)= K s+1/s(s+2) a) What are the open-loop poles and zeros? Plot them on the complex plane as we discussed in class. b) Find the closed-loop transfer function T(s) = C(s)/R(s). c) Solve for the closed-loop poles as a function of K. d) What are the closed-loop poles for K = 0, 1, 10, 100? Plot them on the complex plane as we discussed in class. e) Discuss what happens to each of the closed-loop poles as K increases. Where do they approaches ∞.
The open loop transfer function of DC motor is shown in below. With K = 2 and p = 2. G(s) = K/ s(s+p)(s+20) Design PD controller Gc(s) = Kp + KdS to achieve a percent peak overshoot P.O. ≤ 10% to a unit step input and a settling time (with 2% criteria) Ts ≤ 5 s.
(a) The measured frequency response magnitude and phase of a second order open-loop control system transfer function KG(s) are as shown in Fig. P3a. Determine G(s). (b) A different unit feedback control system has loop transfer function L(s) = C(s)G(s)) = K/s(s+25). The specification for the closed-loop system requires that the percent overshoot to a unit step input to be Mp ≤ 10%. (i) Determine the corresponding specification for the frequency domain resonant peak Mr, the resonant frequency ωr, and the bandwidth ωBW.
The C-V characteristic for an ideal MOS capacitor with cross-sectional area 10^-4 cm2 is shown below. The capacitor has a metal gate, SiO2 gate oxide, and silicon body. (a) Is the substrate doped p- or n-type? Why? (b) Calculate the gate oxide thickness. (c) Calculate the doping concentration in the Si substrate. (d) Draw the energy band diagram of the of the MOS capacitor at point A. (e) Calculate the capacitance (in Farads) at point B.
Assume that ID5 = 100 μA, all transistors lengths are 1.2 μm, and CC = 10 pF. For the two-stage op amp shown above, (a) Estimate the -3 dB frequency of the first stage. (10%) (b) Estimate the unit-gain frequency of the opamp. (5%) (c) Find the slew rate. (5%) (d) What circuit changes could be made to double the slew rate but keep unity-gain frequency and CC unchanged? (Assume all channel lengths are fixed) (5%) (e) Follow (d), how should M6 change to maintain zero systematic offset voltage? (54%) (f) Follow (d) and (e), ignoring the body effect, what is the output voltage range of the opamp? What is the range of common-mode input voltage, assuming ±2.5 V power supplies are used? (10%) [Two-Stage CMOS Op Amp + Output Stage] *n-channel MOS transistors: μnCox = 92 μA/V2; Vtn = 0.8 V; ro = 8,000L (μm)/ID(mA) in saturation region * p-channel MOS transistors: μpCox = 30 μA/V2; Vtp = -0.9 V; ro = 12,000L (μm)/ID(mA) in saturation region
We wish to design the MOS cascode of Fig. 11.95 for an input pole of 5 GHz and an output pole of 10 GHz. Assume M1 and M2 are identical, ID = 0.5 mA, CGS = (2/3)WLCox, Cox = 12 fF/µm2, µnCox = 100 µA/V2, λ = 0, L = 0.18 µm, and CGD = C0W, where C0 = 0.2 fF/µm denotes the gate-drain capacitance per unit width. Determine the maximum allowable values of RG, RD, and the voltage gain. Use Miller’s approximation for CGD1. Assume an overdrive voltage of 200 mV for each transistor.
(a) The MOS capacitor in Fig. 4.1 has VTN = 1 V and VG = 2 V. To what region of operation does this bias condition correspond? (b) Repeat for VG = -2 V. (c) Repeat for VG = 0.5 V. Figure 4.1 MOS capacitor structure on p-type silicon.
Answer the following questions on the circuit shown in Fig. 3. The n-type MOS transistors M1 and M2 have the same characteristics, and the small-signal equivalent circuit of each transistor is shown in Fig. 4. Here, gm, ro, and v are the transconductance, the drain resistance, and the input voltage of the MOS transistor, respectively. RD and RS are the resistances in the circuit. VDD is a positive constant voltage. Note that v1, v2, v3, and v4 represent small-signal components of the voltages V1, V2, V3, and V4, respectively. (1) The small-signal components vin and vout represent the difference of two input signals v1 - v2 and the difference of two output signals v3 - v4, respectively. Find the voltage amplification factor A = vout/vin. (2) The small-signal components vin’ and vout’ represent the sum of two input signals v1 + v2 and the sum of two output signals v3 + v4, respectively. Find the voltage amplification factor A’ = vout’/vin’. (3) Describe in a few lines the function of the circuit in Fig. 3, based on the results of Parts (1) and (2). Assume ro → ∞ and RS ≫ gm-1.