The MOS transistors have the following characteristics: Vtn = |Vtp| = 0.5 V, Kn’ = 400 µA/V2 and Kn’ = 100 µA/V2. Assume VDD = 3 V and Q2 and Q3 are matched. The required gm of the amplifying transistor (Q1) is 1000 µA/V and the output voltage (VOUT ) should be allowed to swing to within 0.2 V of VDD. (a) Find the (W/L) ratio of all transistors and the resistor R. For this part you may assume there is no channel length modulation. (b) Show a clean and labeled small signal equivalent circuit with the values (gm and ra) shown. Assume all transistors have |λ| = 0.02 V-1 (c) Find both an expression and the numerical value for the small signal gain v0/vsig, and Rout. (d) What is the range of the output voltage swing.
Consider a standard CMOS inverter with QN and QP matched and with the input vi rising slowly from 0 to VDD. At what value of vi does the current flowing through QN and QP reach its peak? Give an expression for the peak current, neglecting λn and λp. For kn’ = 500 μA/V2, (W/L)n = 1.5, VDD = 1.3 V, and Vtn = 0.4 V, find the value of the peak current. (Hint: Max current is during switching when for a brief moment, both transistors are in the saturation mode and "half on").
the Q1 transistor has a current ID1 = 100 µA. R = 2kΩ, Assume that Q2 is different from Q1 ( L1 = 2µm and W1 = 4µm, L2 = 1µm and W2 = 6µm). Neglect the channel-length modulation effect (i.e., assume that λ = 0). Find the drain current (ID2) of the Q2 transistor
For the following amplifier, calculate the output voltage, VO, in V. IA = 0.7 mA VB = 1 V VC = 1 VR1 = 3 kΩ R2 = 5.1 kΩ R3= 23 kΩ R4 = 66 kΩ
a. Find the resistor values to meet the specs. You may assume the has transistor β is high for the design, The supply voltage Vcc = 12 V. (20 points) b. Assume the transistor β = 100 and VA = 60 V and Rsig = 5kΩ, Find the transistor small signal parameters (gm, ro, and rbe). Show a clean and labeled small signal equivalent circuit and derive the expression for vo/vsig , Rin and Rout. Now find the numerical values for Rin, Rout, and gain = vo/vsig, (20 points) c. Run a transient simulation of the designed circuit in Multisim. Use the same BJT used in the lab simulation. Show the input voltage vsig and output voltage v0 on the same plot. Choose vsig to be at 1kHz and 10mV peak sinusoidal. Compare with calculated value of gain in part b. (10 points)
9.39 For the op-amp circuit of Fig. P9.39: *(a) Obtain an expression for H(ω) = Vo/Vi in standard form. (b) Generate spectral plots for the magnitude and phase of H(ω), given that R1 = R2 = 100 Ω, C1 = 10 µF, and C2 = 0.4 µF. (c) What type of filter is it? What is its maximum gain? Figure P9.39: Circuit for Problems 9.39 and 9.40.
Consider the CMOS inverter of Fig. 14.22 with QN and QP matched and with the input vI rising slowly from 0 to VDD. At what value of vI does the current flowing through QN and QP reach its peak? Give an expression for the peak current, neglecting λn and λp. For k’n = 500 μA/V2 , (W/L)n = 1.5, VDD = 1.3 V, and Vtn = 0.4V, find the value of the peak current.