A resistively loaded PMOS inverter circuit is shown in figure Q1. The circuit is implemented with the CD4007UBE PMOS. This is essentially the same circuit as the NMOS inverting logic gate you used in Task 3, but with a PMOS transistor instead. The load resistor RD = 6 kΩ, and the supply voltage is VDD = +5 V. The transistor parameters are µpCox = 55 µA/V2, W = 60 µm, L = 10 µm, and Vt,p = -1. For the purposes of this question ignore the channel length modulation effect, i.e. take λ = 0. a) Calculate VOUT as VIN varies from +5 V to 0 V, with 1 V steps, i.e. for 5 V, 4 V, 3 V, 2 V, 1 V and 0 V. b) What is the maximum DC power dissipated by this circuit? Figure Q.1. Resistive load PMOS inverter circuit
Consider the logic inverter shown in Figure 1. If the ON resistance of the NMOSFET is Ron and the threshold voltage of the MOSFET is VTN, accurately sketch the transfer characteristics of the inverter and clearly label the plot with VOH, VIH, VOL, and VIL in terms of the circuit parameters, VDD, VTN, R1, R2 and Ron. Figure 1: Logic Inverter
You come across a nonlinear two terminal device shown in figure 7. The I-V relationship of this device is given by I = I0 e -q(V -V0)/kT 1+e-q(V -V0)/kT. Assume V0 = VDD/2. Your friend Anna Logue suggests you make an amplifier with this using a voltage controlled current source, as shown in figure 7. (a) Nonlinear Device (b) Circuit Using Nonlinear Device Figure 7: Nonlinear Device and a circuit using it for amplification (a) Determine the value of g for which Vout = VDD/2 when Vdc = VDD/2 (b) Determine the incremental output vout resulting from an incremental change in the input vin?
A dynamic logic gate is shown. (a) What is the logic function of the gate at the output of the inverter? (b) What is the purpose of the output inverter? (c) Propose a modification of the circuit to avoid charge sharing. Explain
Consider the inverter below, with pMOSFETs at ID = 1 mA for VOV = 1 V and Vth = 0.5 V. (a) We want to perform load line analysis. Plot ID vs. Vout for all elements for Vin = 1 V on the left plot and Vin = 4 V on the right plot. Label intercepts and intersections, For full credit, label all regions (b) What is the small signal gain for such an inverter? Hint: any answer that ignores the characteristics of the clamped MOSFET is probably insufficient.
One of your friends O. V. Ah makes a PCB with three inverters, but the traces between the power supply and the inverter were too thin and long, resulting in the circuit shown in figure 2. Her board interfaces to a board made by T. Isha. Since it is too late to remake the board, O. V. Ah decides to figure out her worst case VOH and VOL among the three inverters and enforce this on T. Isha's circuit as the static discpline. What values would O. V. Ah calculate given the ON resistance of the N-MOSFET is Ron and the threshold voltage of the MOSFET is VTN ? Figure 2: A chain of inverters on a PCB
Shown below is the energy band diagram of a MOS-device. Answer the following questions. Again, lack of proper explanation will get you no credit. Semiconductor bandgap = 1 eV and intrinsic carrier concentration is 10^10 cm^-3 1. Is this a PMOS or NMOS? Explain. 2. Is the device in accumulation, depletion or inversion? Explain. 3. What is gate voltage (state both magnitude and sign with correct explanation) 4. What is the doping density in the semiconductor bulk? 5. Are the dopants donors or acceptors? 6. If the electric field in the insulator is 3 MV/m, what is the surface potential φ5?
Sometimes it is useful to have a logic circuit which has a two different thresholds for turning on and off the circuit depending on the state of the output (and in turn the input). This circuit goes by the name Schmitt trigger and an NMOS version is shown in figure 4. Determine for what voltage level at A will the circuit output a logic high when A swings from 0 V to VDD. What is the voltage at A for which the circuit will output a logic low if A swings from VDD to 0 V? Assume the ON resistance of all the N-MOSFETs are Ron and the threshold voltage of the MOSFETs are VTN. Figure 4: Schmitt Inverter
Rather than use transistors your friend W. Too wants to use diodes to implement logic gates. He shows you the circuit he designed shown in figure 5. If A and B can swing all the way from 0 V to VDD, does the circuit implement a logic gate? If so what gate is it and what is its static discipline? Assume the diode is modeled by an ideal diode with a series resistance RD Figure 5: Diode Based Logic Gate
An enhancement load pMOS inverter is shown below: Similarly: i) Graph the voltage-voltage transfer characteristic (Vi-Vo) for this circuit assuming that VDD ≤ Vi ≤ VSS. For each region of operation, calculate the output voltage in terms of the input voltage and the circuit parameters. ii) Hence or otherwise, estimate the static voltage characteristics, V max iL, V min iH, V max oL and V min oH. iii) If kp = 100 µAV-1, VT = 1 V and VDD = 10 V, calculate the voltage where Q1 is transitioning from saturation to the linear mode. Clearly identify the model of each component used.