The amplifier provided is biased to operate at gm = 1 mA/V with RD = 11 kΩ, and Rs = 9 kΩ. Assuming ro = ∞, find: 1. the mid-band gain AV = V0/Vi 2. and the value of Cs that places fL at 40 Hz.
For the given amplifier: 1. Determine the value of RF required for a closed loop gain ACL = V0/lS = -15 kV/A. 2. Calculate the input resistance Rin. 3. Calculate the output resistance Rout. Assume ideal open loop behavior with the following circuit parameters: • gm = 25 mS • r0 = ∞ RF = kΩ Rin = kΩ Rout = kΩ
A MOSEFT transistor with an ideal current source as the load with I = 2 mA. The source is grounded, VDD = 9 V, Vt = 1 V, k = 0.2 mA/V2, VA = 75 V. If a load resistor of 20 K is connected to the drain through a large capacitor, and the current source is modeled as a 50 K resistor, what is the voltage gain? (include sign)
It is required to activate row 3 in the dynamic row address decoder shown. Write the suitable inputs to bit lines 1, 2, 3, and 4
One of your friends who loves the history of science D. Amin Poor, comes across the circuit implementation of the first neural network the Perceptron using the McCulloch & Pitts neuron shown in figure 3. He knows the circuit is a universal approximator but is confused about how to make the circuit implement an NAND gate. He comes to you for help since you are an expert in circuits. Can you choose the values of R1, R2, R3, RB, VTN, and VB so that the circuit implements an NAND gate? If an exact value cannot be determined express it as a range. Assume the ON resistance of the N-MOSFET is Ron and the threshold voltage of the MOSFET is VTN. VB is a bias voltage not an input. Figure 3: A circuit approximation of the McCulloch and Pitts Neuron
Fig. 13 (a) represents a source follower biased by an ideal current source I1. VDD = 3.3 V, gm1 = 2 mA/V,RL = 1 kΩ, CC = 10 nF (a) Determine the corner frequency (Hz) of the HPF characteristic of the transfer function of the amplifier. (b) Let's suppose the input of Fig. 13(b) is applied. Plot Vout (t). Specify Vout at t = 0+, 10 μs, and 20 μs in the plot.
Give the truth table for the following transistor level schematic. Explain the source of "good logic 0’s i.e., GND" and "good logic 1 ’s i.e., VDD" (using the labels P1, P2, N1 and N2) at C under each of the four input conditions ( AB = 00, 01, 10, 11). A B OUT Source of Good Logic 0 at C Source of Good Logic 1 at C 0 0 0 1 1 1 1 0
Consider the CMOS SRAM cell in the figure during the read operation. Assume that Q = 1, and bit lines are precharged to VDD/2. Ignore the body effect. Process parameters: VDD = 5 V, VTN = -VTP = 1 V, KN = 120 μA/V2, KP = 40 μA/V2, CB = 50 pF. Assuming M5 and M6 drain currents to be constant with initial values, how long (ns) will it take to develop 25mV differential voltage difference between the bit lines? Choose the closest value. a. 0.5 b. 5 c. 1 d. 2 e. 4
5.185. (a) Find the Q-points of the transistors in the CMOS amplifier in Fig. P5.185 if the supply voltage is 1.5 V, VTN = 0.6 V, VTP = -0.6 V, RG = 1 MΩ, Kn = Kp = 50 μA/V2, n = 1.5, and T = 300 K. (b) Repeat for the circuit for RG = 5.1 MΩ. (c) Repeat (a) for VDD = 3.3 V.
Consider the circuit shown in Fig. 1. a) Assume both transistors are in saturation. Find lD1’s expression in terms of VDD and RB, μn, Cox, VTH1, and W1/L1. b) As shown in the circuit, M’s Gate is connected to M2’s Gate, and the Source terminal of the two devices are also connected to the same terminal (i.e., ground). If the two transistors have the same μn, Cox, VTH, and W/L, what is the relationship between ID1 and ID2? c) What will be the relationship if W2/L2 = 5*W1/L1? d) Try to draw a circuit with similar functionality but using two PMOS transistors instead of two NMOS transistors. Fig.1. Circuit schematic of a current mirror implemented using two NMOS transistors.
Consider the dynamic amplifier shown below. Supply voltage is VDD = 1.8 V. MOSFETs S1, S2, and S3 are ideal analog switches. They are controlled by ϕ1, which changes from 0 V to VDD at t = 0. MOSFETs M1 and M2 are biased in the active (saturation) region. Their transconductances are gm1 = gm2 = 0.5 m℧. Define Vid = Vi1 - Vi2 Vic = Vi1 + Vi2/2 Vod = Vo1 - Vo2 Voc = Vo1 + Vo2/2 The amplifier is activated at t = 0. The amplification time Ta is the time for Voc falling from VDD to VDD - 0.6 V. a. [7pts] Find Ta. b. [8 pts] Find the differential voltage gain Adm = Vod/Vid at t = Ta.
For the following circuit, VDD = 2 V, VBE = 0.7 V, VX = 0.8 V, kn = 20 mA/V2, IS = x fA (see below), γ = 0.25, λ = 0.3, VA = 20 V VT = 25.9 mV, 2ϕF = 0.8 V, VTH0 = 0.35 V, R1 = 20 kΩ are given. Find the values of R2 and R3. Is = 3.5 fA
For the shown amplifier, RD = 1kΩ, Rs = 50Ω, and VDD = 6V. The NMOS device parameters are as follows: K1 = 1/2kn’(W/L)M1 = 4 mA/V2, K2 = 1/2kn’(W/L)M2 = 1 mA/V2; where kn = KP = μn⋅Cox Assume that the Early voltage magnitude is infinity (λ = 0) for the transistors, and that the threshold voltages are Vto = 1 V. a) Find the DC bias voltage VB that establishes a DC operating point with Vout (DC) = 5 V. (6 points) VB= b) Calculate the small-signal transconductances (gm1, gm2) of transistors M1 and M2. (4 points) gm1 = , gm2 = c) Draw the small-signal equivalent circuit. (5 points) d) Derive the equation (in terms of small-signal model parameters and resistors as variables) for the small-signal voltage gain (Avs = Vout/Vs) and calculate its value. Assume that the coupling capacitor has a large value. (10 points) Avs =