For an NMOS differential pair, let VDD = VSS = 2.5 V, kn’W/L = 3 mA/V2, Vtn = 0.7 V, I = 0.2 mA, RD = 5 kΩ, and neglect channel-length modulation. With G2 grounded and vG1 = vid. Let vid be adjusted to the value that causes iD1 = 0.11 mA and iD2 = 0.09 mA. Find the corresponding values of vGS2, vs, vGS1, and hence vid. What is the difference output voltage vout = vD2 - vD1 ? What is the voltage gain (vD2 - vD1)/vid ? What value of vid results in iD1 = 0.09 mA and iD2 = 0.11 mA ?
For an NMOS differential pair with a common-mode voltage VCM applied, as shown below. Let VDD = VSS = 1.0 V, kn’ = 0.4 mA/V2, (W/L) = 12.5, Vtn = 0.5 V, I = 0.2 mA, RD = 10 kΩ, and neglect channel-length modulation. (a) Find VOV and VGS for each transistor. (b) For VCM = +0.3 V, find VS, ID1, ID2, VD1, and VD2. (c) What is the highest value of VCM for which Q1 and Q2 remain in saturation? (d) If current source / requires a minimum voltage of 0.2 V to operate properly, what is the lowest value allowed for Vs and hence for VCM ?
The shown configuration has E-NMOS with Vt = 1 V and D-NMOS load with Vt = -1 V connected to VDD = 5 V, if the input voltage (Vi) is 0.5 V the output voltage (v0) is: (a) 0 V (b) 5 V (c) 4 V (d) 1 V
Suppose VDD = 1.2 V and Vt = 0.4 V. Determine Vout in the figure for the following: a. Vin = 0 V b. Vin = 0.6 V c. Vin = 0.9 V d. Vin = 1.2 V
For the MOSFET bias circuit shown, what is the drain current, Id, in milliamps? Assume that the transistor is in the saturation region, and use: Vdd = 14 V, Rg1 = 50.8kΩ, Rg2 = 45.9kΩ, Rd = 2.9kΩ, Rs = 6.1kΩ, Vt = -0.5 V, and |Von| = 0.17. (Remember that |Von| = |Vov| = |Vgs| - |Vt|) Neglect the effect of channel-length modulation and body effect.
We observe that NFETs do not transmit a ‘1’ very well and PFETs do not transmit a ‘0’ very well because with VGS = VDD and VDS = VDD in an NFET, the Source terminal will charge up only until it reaches VDD-VTn because at higher voltages, the Gate-Source voltage difference is less than the Threshold Voltage VTn of the NFET causing it to ‘turn-off’ when the Source Terminal rises to within a VTn of VDD. Sketch the output voltage characteristic if the PFET and the NFET positions were swapped as shown below? i) Write down the voltages at A, B, C, D, E, F, G in the following circuit, assuming that the initial voltage on each node is 2.5 volts. The relevant transistor parameters are, VDD = 5 V, VTn = 1 V and ∣VTp∣ = 0.7 V
For an NMOS differential pair, It VDD = VSS = 2.5 V, kn’W/L = 3 mA/V2, Vtn = 0.7 V, I = 0.2 mA, RD = 5 kΩ, and neglect channel-length modulation. Let vG2 = 0 and vG1 = vid. Find the value of vid that corresponds to each of the following situations: a) iD1 = iD2 = 0.1 mA b) iD1 = 0.15 mA and iD2 = 0.05 mA c) iD1 = 0.2 mA and iD2 = 0 mA d) iD1 = 0.05 mA and iD2 = 0.15 mA e) iD1 = 0 mA and iD2 = 0.2 mA For each case, find vS, vD1, vD2, and (vD2 - vD1)