In the above circuit VDD = 5 V. The process conduction parameter for all three MOSFETs is kn’ = 2mA/V2. The aspect ratio for the n-channel depletion type MOSFET ML is (W/L)L = 1. The threshold voltage for the n-channel depletion type MOSFET ML is VTNL = -0.6 V. The aspect ratio for the n-channel enhancement type MOSFET MD1 is (W/L)D1 = 4. The aspect ratio for the n-channel enhancement type MOSFET MD2 is (W/L)D2 = 2. The threshold voltage of the both n-channel enhancement type MOSFET MD1 and MD12 is VTND = 0.4V. Let V1 = 0 V and V2 = 5 V. Find the output voltage vO in mV. Find the current iDL in mA. Find the current iD1 in mA. Find the current iD2 in mA. Find the power dissipation in mW.
Assumptions for all problems (unless specified otherwise, give answers to 10% ): VDD(V) VT0( V) Body effect γ(V 0.5 ) VDSAT( V) k’ (A/V 2) λ(V -1 ) NMOS 2.0 0.4 0 0.5 500×10-6 0 PMOS -0.4 0 -0.5 -200×10-6 0 1. All transistors have the minimum length (Lunit = 250 nm) 2. Ignore body effect and channel length modulation 3. A transistor's intrinsic capacitance (cap) and gate cap are equal, i.e., Cint = Cg, γ = 1 4. The unit-sized transistor has Wunit = Lunit and intrinsic cap Cint = Cg = Cdb = Csb = 1.0fF. 5. For the unit sized inverter, β = (W/L)P / (W/L N = WP/WN = 2, WN = L = 250 nm 6. The unit sized transmission gate has a resistance Req,tr = 10kΩ and all caps of 1.0fF. a) (6 pts) How does the following circuit operate? In a few words/charts, describe what it does Sketch the waveforms of nodes X and Q given the inputs shown below. Initial state of signals X and Q are unknown (mark with xxx as needed) until the impact of the input signals propagate. X Q b) (4 pts) How would you size each transistor? Match the 2:1 inverter (including the clock). Draw the sizing next to the schematic. Calculate the switch model equivalent resistance(s) (note the equation given at the front of the exam for Req, switch model capacitance(s) (based on your sizing), and worst-case propagation delay through the circuit, max(tpLH,tpLH), where output is taken from Q and inputs are IN1 and IN2. c) (4 pts) Calculate the energy consumption from the VDD power supply of this circuit for the input pattern and time duration given in the timing diagram (previous page). Ignore the energy consumption related to driving IN1, IN2, and CLK. State any assumptions you need to make to determine a numerical value.
The following circuit diagram shows the use of two such MOS transistors for the implementation of a fundamental logic gate in digital ICs. Both MOS transistors (M1 & M2) have the same threshold voltage VT = 0.5 V and µCox = 10-4 A/V2. Fig. 2.1 (a). What are the operation modes of the MOS transistors (MI&M2) when the input is a logic “low” signal (i.e. Vin = 0 V )? (b). Find out the expression of the current flowing through the MOS transistor M2 as a function of the output voltage Vout. Then determine the current when Vout = 1.5 V. (c). Using results in (a) and (b) as a hint, hence or otherwise, determine VOH (i.e. the maximum output voltage when the output is a logic “high” signal). (d). Based on the results in (b) and (c), hence or otherwise, describe two advantages of digital circuits with CMOS implementation compared with the implementation in Fig. 2.1. (e). Draw a schematic circuit diagram of the CMOS implementation of the logic circuit in Fig. 2.1. You must use standard circuit symbols and show the signal interconnections clearly with proper labels.
A transistor schematic diagram of a digital circuit is shown below (Fig. 3.1). The sizes of the MOS transistors are given as (W/L)l = (W/L)2 = 16 and (W/L)3 = 4 with VT n = 0.5 V and µnCox = 10-4 A/V2. VDD = 1.8 V. Fig. 3.1 (a). What logic gate is the above digital circuit? Draw the logic gate symbol of the above digital circuit. (b). Determine the approximate output voltage Vout for the following given input voltages Vin1 and Vin2 in the static case. Vin1 (V) Vin2 (V) Vout (V) 0 0 0 3.0 3.0 0 (c). When both the inputs Vin1 and Vin2 are connected to VDD, determine the output voltage Vout. (d). Now, only the p-type MOSFETs with |V T p| = 0.5 V and µpCox = 5 × 10-5 A/V2 are available. Draw a schematic circuit diagram of such a logic gate implemented using only p-type MOSFETs. You must use standard circuit symbols and show the signal interconnections clearly with proper labels.
An NMOS transistor in the amplifier circuit of Fig. 2 has Vt = 1 V, kn = 4 mA/V2. Assume VDD = 10 V, RG1 = 6MΩ, RG2 = 4MΩ, RS = 1kΩ, and RD = 2kΩ. (a) (10 points) Neglect the channel-length modulation and body effect. Find the voltage VGS and the drain current ID. Then, find gm. (b) (10 points) Find ro if VA = 100 V. Then, find the resistance Rod looking into the drain terminal of NMOS and the voltage gain vo/vsig.
The NMOS transistors Q1 and Q2 in Fig. 4 having gm = 1 mA/V are operated in saturation. Ignore the channel-length modulation and body effects for these devices. Assume VDD = 5 V and VSS = -5 V. (a) (10 points) Find the open-circuit voltage gain, vs1/vi, and output resistance Ro1. (b) (10 points) Find the input resistance Ri2 and the voltage gain, vo/vi2. (c) (10 points) Now, if the voltage node vs1 is connected to the node vi2, find the overall voltage gain, vo/vi.
A transistor schematic diagram of a digital circuit is shown below (Fig. 2.1), with the MOSFET parameters µCox(W/L) = 100 µA/V2 and |VT| = 0.7 V. The supply voltage VDD is 3.0 V. Fig. 2.1 (a). What logic gate is it shown in Fig. 2.1? Draw the logic gate symbol of the above digital circuit. (b). What are the operation modes of the MOSFET M1 for the input voltage Vin = 0 V, 2.0 V and 3.0 V ? (c). Sketch a graph showing the static voltage transfer characteristics (VTC) (i.e. Vout versus Vin ) of the logic circuit (Fig. 2.1). Any turning point(s) or important features (e.g. voltage levels) as well as axes must be shown clearly or labelled explicitly. On the same graph, sketch a second curve if RL = 100 kΩ and a third curve if RL = 4 kΩ. (d). Now, instead of using a load resistor, a depletion-mode MOSFET of the same type is used for implementing the logic gate in addition to the originally given MOSFET. Draw a schematic circuit diagram of such an implementation using two MOSFETs.
Two CMOS inverters are connected together as shown below (Fig. 2.1). If it is needed in calculations, please use the following assumed data: gate oxide thickness tox = 7.6 nm for silicon dioxide (SiO2); built-in voltage V bi = 0.7 V; zero-bias bottom-area junction capacitance (normalised) Cj0An = 1.10 × 10−4 F/m2 ; zero-bias sidewall capacitance (normalised) Cj0swn = 2.19×10−11 F/m; state your assumption clearly if other additional data are needed. Sizes of M1 to M4 : Fig. 2.1 (W/L)n = 0.4µm/0.2µm (W/L)p = 1.0µm/0.2µm (a). With the input waveform shown in Fig. 2.1, at time t1, what are the expected operation modes respond to the given input waveform. (b). Determine the dominant drain capacitance of M2 at time t1. Assume the worst case of the sidewall capacitance contributed from four sides. (c). Determine the dominant gate capacitance of M3 at time tl. (Hint: the bulk terminal of each of the MOSFET is connected to either ground or VDD). (d). Draw a sketch comparing the output waveform with the input signal, taking into account the qualitative effects of capacitance within the MOS transistors.
Kn = 200 µA/V2 , Kp = 50 µA/V2, VTHN = 1 V, VTHP = 1 V, (W/L)N = 10/1, (W/L)P = 40/1, λn = λp = 0.1 V-1 a) find Vx, Vy, Ix, Iy b) find Av,dm = vout/vin c) find Av,cm = vout/vc (vc : input of small signal common mode) d) find CMRR = Av,DM/Av,CM
Question 9: cMOS, switching power An IC with a switching rate of 1 GHz and VDD = 5 V is dissipating 40 W. What will be the power dissipation if we change VDD to 3V and the switching rate to 5 GHz while keeping the activity factor the same? Pnew = number (rtol = 0.01, atol = 1e-05)
In the circuit below, M1 operates at 600 mV away from triode region. Assume that W/L = 80, λ = 0, VDD = 5 V, I1 = 2 mA, R1 = 32 kΩ, RD = 1.5 kΩ, RL = 900Ω, and RSig = 1 kΩ. a. Draw the DC circuit and determine the drain current ID, the value of R2, and the transconductance gm for M1. b. Draw the AC circuit and determine the voltage gain Av, the I/O impedances Rin (including RSig) and Rout for the circuit.
The NMOS transistor in the CS amplifier shown in Fig. 3 has Vt = 0.7 V and VA = 50 V. a. Neglecting the Early effect, verify that the MOSFET is operating in saturation with ID = 0.5 mA and VOV = 0.3 V. b. What must the MOSFET’s K be? c. What is the dc voltage at the drain? d. Find Rin and Av Fig. 3: A NPMOS circuit for problem 3.
Design the nMOSFET based circuit such that it is in the saturation mode of operation for DC bias condition. Be sure to show your work and write neatly. (Hint: make sure to use the correct characteristic equation when formulating the problem and equations, refer to notes and book) Design Contraints: Vdd = +20 V, Kn = 40uA/V2, λ = 0, VTN = 1 V, ID = 2 mA A. Find the DC equivalent circuit B. Determine the set of simutaneous equations C. Find resistor values (Z1, Z2, Z3, Z4) based on desired mode of operation, design contraints, and equations (part B) D. Find the AC equivalent circuit E. Determine the transfer function and gain value |T(s)| for your design. (Hint: you need to calculate the transconductance, gm) F. What would the resistor values (Z1, Z2, Z3, Z4) need to be such that the gain for the AC operation of the device is |T(s)| = 2.5 ? Show your work. Be sure to include design constraints such that the device is still in saturation mode of operation.
Consider a circuit shown in the Figure with 2 transmission gates and 2 capacitors. The values of capacitors are C1 = 125fF and C2 = 48fF. For the circuit, we have the following initial and final states. • Vin = VDD = 3.3 V • At time, t < 0, (x, y) = (1, 0) • At time t = 0, the signals are changed to (x, y) = (0, 1). • Assume initial V2 = 0.22 V across C2. (A) (5pts) Charge across C1; (B) (5pts) Charge across C2; and (C) (10pts) Compute the final value of voltage (V2) across C1 and C2 after charge sharing has taken in place. Show all your work. An answer without clear work will not be considered. Answer: (A) Q1= ; (B) Q2 = ; (C)V2 =
Consider the circuit below. Assume ITAIL = 1 mA, RD = 1 kΩ, VDD = 3 V The input/output transfer characteristic of the circuit is on the right. a) Indicate the values of VH, VL and VMID. b) Indicate the slope of the line in terms of small signal parameters and other element values. c) Label which curve corresponds to V01 and which to V02.
Draw the circuit diagram of a CMOS gate (showing all the transistors) which implements the logic function ((A + B + C) • D) + E b. (15pt) On the circuit diagram show the sizes of the NMOS and PMOS devices so that the network has approximately the same worst case tpHL and tpLH as an inverter (with an NMOS W = 5µm and PMOS W = 11µm.) which is driving an equal capacitance. Assume that self-capacitances are negligibly small compared to the load capacitance. Avoid increasing the area unnecessarily.
Given the following circuit, assume that all of the circuit’s inputs are initially zero during the pre-charge phase and that all internal nodes are at 0 V. 1. Calculate the voltage drop on V0, if A changes to 1 (VDD = 2.5 V) during the evaluate phase. It is given that Vtn 0 = 0.5 V, 2ϕF = 0.6 V, and γ = 0.4 V1/2. Hint: Don’t forget the body effect. 2. Now calculate the voltage drop on Vo if both A and B change to 1 (under the above conditions). Determine the maximum number of transistors that can be connected in series to M1 and M2 (including M1 and M2, excluding M0) if the output should not fall below 0.9 V during the evaluate phase. Assume that each one of the new transistors has the same intrinsic capacitance (to ground) as M1 and M2 (C=10fF).
Design an operational transconductance amplifier (OTA) shown in Fig. 2, to satisfy the following specifications: gain bandwidth product (GBW) is 100M Hz for CL = 2p F, bandwidth is 1MHz, VDD = 1.8 V, Vtn = |Vtp| = 0.45 V, µnCox = 270 µA/V2, µpCox = 65 µA/V2, and λN = λP = 0.08 V-1 . For simplicity, you may operate all devices at the same overdrive voltage (VOV ), neglect body effect, and velocity saturation effect. Determine the currents, (W/L) ratios of the MOS transistor, and input common-mode range (ICMR) of the amplifier. 1. W L ratios of transistors and IBIAS • [(3 + 3 + 3 + 3 =)12pts] (W/L )M1,2 = ; (W/L)M3,4 = (W/L)M5,6 = ; IBIAS = 2. ≤ VICMR ≤ [6 pts] 3. ≤ Vout ≤ [4pts] 4. Total power dissipation. Pdiss = [2pts] 5. Identify vin(+) and vin(-) in Fig. 2. [1 pts] Figure 2: Transconductance amplifier.
A cascode current mirror circuit is shown in Fig. 3. The device parameters are given as µnCOX = 300 µAV -2, VDD = 1.8 V, IREF = I0 = 12 µA, λN = 0.08 V-1 , Vtn = 0.5 V, overdrive voltage VOV = 0.2 V, γ = 0, and neglect velocity saturation effect. 1. Determine the minimum output voltage. [2 pts] Answer: V 2. Mark each node voltages (in V) of the current mirror circuit. [3 pts] 3. Determine W/L ratio of M3 transistor in order to obtain the minimum output voltage. [3 pts] Answer: W/L = 4. Determine R1 in the current mirror circuit. [3 pts] Answer: Ω 5. Determine Rout of the current mirror circuit. [3 pts] Figure 3: Current mirror circuit. Answer: Ω
Given the circuit diagram in the figure, find the following voltages: Vda, Vbh, Vgc, Vdi, Vfa, Vac, Vai, Vhf, Vfb, and Vdc. Let's start with some easy voltages first. What is voltage Vef? What is voltage Vde? What is voltage Vbe? What is voltage Vda? Now, using the previous answers, let's find: Vbh, Vgc, Vdi, Vfa, Vac, Vai, Vhf, Vfb, and Vdc.
Given the resistor configuration shown in the figure, find the equivalent resistance between the following sets of terminals: (1) a and b, (2) b and c, (3) a and c, (4) d and e, (5) a and e, (6) c and d, (7) a and d, (8) c and e, (9) b and d, and (10) b and e. First, find: Rab (the resistance from a to b), Rbc and Rac. Now find: Rde (the resistance from d to e), Rae, Rcd, Rad, Rce, Rbd, and Rbe.
Find the value of k in the network in the figure such that the power supplied by the 6-A source is 120 W.
In the network in the figure below, find Io using superposition. Io with only Va turned on = mA Io with only Ia turned on = mA Io = mA
Find Io in the network in the figure below using Thévenin's theorem. Break the network at the 1k Ohm resistor containing I0. Vth = V Rth = kΩ Io = mA
Find Io in the network in the figure below using Thévenin’s theorem. Break the network at the 5k Ohm resistor containing I0. Vth = V Rth = kΩ Io = mA
If a 7-kΩ load is connected to the terminals of the network in the figure below, VAB = 4.28 V. If a 18-kΩ load is connected to the terminals, VAB = 6.83 V. Find VAB if a 29-kΩ load is connected to the terminals. Vth = V Rth = kΩ VAB across 29 kΩ load = V
Use Norton's theorem to find Vo in the network in the figure below. Break the network just to the left of the 8 mA current source, i.e. separate the 8 mA source and 2 Ohm and 6 Ohm resistors from the rest of the network. IN = mA RN = kΩ Vo = V
Find the Thévenin equivalent of the network in the figure below at the terminals A-B. Apply a 1 mA source at the terminals A-B. VTh = V RTh = kΩ
In the network in the figure below, find RL for maximum power transfer and the maximum power transferred to this load. First find the Thevenin Equivalent Resistance. RTH = kΩ
The current in a 100-mH inductor is i(t) = 9 sin371t A. Find (a) the voltage across the inductor and (b) the expression for the energy stored in the element. (a) v(t) = cos t V (b) w(t) = sin2 t J
The current in a 20-mH inductor is given by the expressions i(t) = 0 t < 0 i(t) = 11(1-e -t) mA t > 0 Find (a) the voltage across the inductor and (b) the energy stored in it after 1 s. (a) v = V t < 0 e -t μV t > 0 (b) w(1) = μJ
If the total energy stored in the circuit in the figure below is 400 mJ, what is the value of L? mH
Given the network in the figure, find (a) the power dissipated in the 2-Ω resistor and (b) the energy stored in the capacitor. (a) W (b) J
Given a 5-, 15-, and 20-μF capacitor, can they be interconnected to obtain an equivalent 10-μF capacitor?
The three capacitors shown in the figure below have been connected for some time and have reached their present values. Find (a) V1 and (b) V2. (a) V1 = V (b) V2 = V