Figure 0.3 shows NMOS and PMOS devices with drains, source, and gate ports annotated. Determine the mode of operation (saturation, linear, or cutoff) and drain current ID for each of the biasing configurations given below. Verify with SPICE. Use the following transistor data: NMOS: k’n = 115 µA/V2 , VT0 = 0.43 V, λ = 0.06 V–1, PMOS: k’p = 30 µA/V2 , VT0 = –0.4 V, λ = -0.1 V–1. Assume (W/L) = 1. a. NMOS: VGS = 2.5 V, VDS = 2.5 V. PMOS: VGS = –0.5 V, VDS = –1.25 V. b. NMOS: VGS = 3.3 V, VDS = 2.2 V. PMOS: VGS = –2.5 V, VDS = –1.8 V. c. NMOS: VGS = 0.6 V, VDS = 0.1 V. PMOS: VGS = –2.5 V, VDS = –0.7 V
For the op amp circuit of Fig. 7.138, let R1 = 10 kΩ, Rf = 30 kΩ, C = 20 μF, and v(0) = 1 V. Find v0.
In the above figure, vl is a square wave, ranging from 0 to VDD at frequency fCLK. In this problem, choose from the following list the largest fCLK value that may be used if the inverter's propagation delay is not to exceed one-eighth of a clock period. 500 MHz 1 GHz 2 GHz 8 GHz 4 GHz MOSFET Parameters: Electrically-matched devices Kn = Kp = 20 μA/V2 VTN = -VTP = 300 mV λn = λp = 0 V-1
Consider the circuit configuration of Figure 0.5. a. Write down the equations (and only those) which are needed to determine the voltage at node X. Do NOT plug in any values yet. Neglect short channel effects and assume that λp = 0. b. Draw the (approximative) load lines for both MOS transistor and resistor. Mark some of the significant points. c. Determine the required width of the transistor (for L = 0.25 µm) such that X equals 1.5 V. d. We have, so far, assumed that M1 is a long-channel device. Redraw the load lines assuming that M1 is velocity-saturated. Will the voltage at X rise or fall?
In the circuit of Fig. 4.48, IS1 = IS2 = 3 × 10-16 A. (a) Calculate VB such that IX = 1 mA. (b) With the value of VB found in (a), choose IS3 such that IY = 2.5 mA.
If v(0) = 10 V, find vo(t) for t > 0 in the op amp circuit in Fig. 7.132. Let R = 100 kΩ and C = 20 µF.
In the amplifier below, VTH = 0.5 V and λ = 0 for all the transistors, β1 = β3 = β5 = 2 mA/V2, β2 = β4 = β6 = 0.5 mA/V2, and VDD = 4 V. Resistors and capacitors are used for biasing purposes, and may be assumed to be very large. a. Find the operating point of the transistors. b. What is the overall small signal gain of the amplifier (vo/vi)?
Sketch IX and the transconductance of the transistor as a function of VX for each circuit in Fig. 2.48 as VX varies from 0 to VDD.
In the circuit shown in the figure, vi is a triangular wave. Find the largest peak output amplitude, VO, that can be used if the output waveform is to be an undistorted triangular wave of ±VO volts as shown. 14 V 12 V 5 V 15 V 10 V Op-amp Parameters: ft = 3 MHz SR = 5 V/µs Vo max = ±14 V io max = ±15 mA
Determine vo(t) for t > 0 in the circuit of Fig. 7.139. Let is = 10u(t) μA and assume that the capacitor is initially uncharged.
An NMOS device is plugged into the test configuration shown below in Figure 0.4. The input Vin = 2 V. The current source draws a constant current of 50 µA. R is a variable resistor that can assume values between 10 kΩ and 30 kΩ. Transistor M1 experiences short channel effects and has following transistor parameters: k’ = 110*10-6 V/A2, VT = 0.4 , and VDSAT = 0.6V. The transistor has a W/L = 2.5µ/0.25µ. For simplicity body effect and channel length modulation can be neglected. i.e λ=0, γ=0.
In the circuit of Fig. 4.49, it is observed that the collector currents of Q1 andQ2 are equal if VBE1 - VBE2 = 20 mV. Determine the ratio of transistor cross section areas if the other device parameters are identical.
The op amp used in the above circuit is considered to be an ideal device. Choose the correct output waveform for the circuit, given the input waveform shown.
Sketch Vout as a function of Vin for each circuit in Fig. 2.49 as Vin varies from 0 to VDD.
Given the data in Table 0.1 for a short channel NMOS transistor with VDSAT = 0.6 V and k’ = 100 µA/V2, calculate VT0, γ, λ, 2|φf|, and W/L: Table 0.1 Measured NMOS transistor data
This question: Moore’s law predicts that the number of transistors on an integrated circuit doubles every two years. If the microprocessor shown above dissipates 60 watts at VDD = 3 V, then find the value of VDD that will be required for the next-generation microprocessor in 4 years with transistors working at doubled frequency (2 times). Assume the device capacitance remains constant and that we want the power dissipation to remain unchanged at 60 watts. 1.5 V 530 mV 750 mV 1.06 V 864 mV
Consider the following stick diagram of a CMOS design. A. Draw the equivalent transistor level schematic? Make sure to follow the right order of the transistors (closest to output, closest to ground...etc) B. Write the implemented logical expression for Y ? C. Size the transistors in your design with a Wp/Wn = 3/2 ratio? D. Estimate the area in terms of Lambda, if track length is 6-Lambda? E. If this was a 100 nm technology, what is the area of the circuit?
Sketch VX and IX as a function of time for each circuit in Fig. 2.51. The initial voltage of C1 is equal to 3 V. In part (e), assume that the switch turns off at t = 0.
The circuit of Figure 0.6 is known as a source-follower configuration. It achieves a DC level shift between the input and output. The value of this shift is determined by the current I0. Assume γ = 0.4, 2|φf| = 0.6 V, VT0 = 0.43 V, k’ = 115 µA/V2, and λ = 0. The NMOS device has W/L = 5.4µ/1.2µ such that the short channel effects are not observed. a. Derive an expression giving Vi as a function of Vo and VT(Vo). If we neglect body effect, what is the nominal value of the level shift performed by this circuit. b. The NMOS transistor experiences a shift in VT due to the body effect. Find VT as a function of Vo for Vo ranging from 0 to 1.5V with 0.25 V intervals. Plot VT vs. Vo. c. Plot Vo vs. Vi as Vo varies from 0 to 1.5 V with 0.25 V intervals. Plot two curves: one neglecting the body effect and one accounting for it. How does the body effect influence the operation of the level converter? At Vo (body effect) = 1.5 V, find Vo (ideal) and, thus, determine the maximum error introduced by body effect.
Consider the circuit shown in Fig. 4.50. (a) If IS1 = 2IS2 = 5 × 10-16 A, determine VB such that IX = 1.2 mA. (b) What value of RC places the transistors at the edge of the active mode?
In the circuit to the right, a CMOS inverter is used to control an LED lamp. VDD = 3 V. Suppose VTN = |VTP| = 1.5 V. RON_N = 400 Ω; RON_P = 600 Ω. C = 0.005 F. The lamp has an internal resistance RL = 400 Ω and needs a voltage > 1 V to light up. Both the NMOS and PMOS can be treated with SR model. Suppose initially Vin = 0 (for a long time). (1) (2pts) When Vin = 0, is the lamp ON or OFF? (show your analysis) (2) (4 pts) Suppose at t = 0,Vin now changes from 0 to 3 V, calculate how long it takes for the lamp to change its initial state in (1) (3) (2 pts) How much energy ( E ) is dissipated during the process in (2) (i.e., from t = 0 till the lamp changes its state).
In this question, if we triple (3 times) VDD and double the clock frequency in the CMOS microprocessor shown, then by what factor does the power dissipation increase?
Design the inverter circuit in the below figure to provide VDD = 1.2 V, VOL = 50 mV, and so that the current the supply in the low-output state is 30 μA. The transistor has Vt = 0.4 V, μnCox = 500 μA/V2, and λ = 0. (a) Determine the required values of rDS, RD, and W/L. (b) How much power is drawn from the supply when the output is low? (c) How much power is drawn from the supply when the output is high?
Sketch VX and IX as a function of time for each circuit in Fig. 2.52. The initial voltage of each capacitor is shown.
D 7.103 Figure P7.103 shows a variation of the feedback-bias circuit of Fig. 7.52. Using a 3-V supply with an NMOS transistor for which Vt = 0.8 V, kn = 4 mA/V2, and λ = 0, provide a design that biases the transistor at ID = 0.5 mA, with VDS large enough to allow saturation operation for a 1-V negative signal swing at the drain. Use 13 MΩ as the largest resistor in the feedback-bias network. What values of RD, RG1, and RG2 have you chosen?