The electron concentration in a region of silicon is shown in Fig. P2.44. (a) If the electron mobility is 350 cm2/V•s and the width WB = 0.25 µm, determine the electron diffusion current density. Assume room temperature. (b) Plot the electron velocity for 0 ≤ x ≤ WB.
The circuit of Fig. P2.2 uses an op amp that is ideal except for having a finite gain A. Measurements indicate vO = 4.0 V when vI = 1.0 V. What is the op-amp gain A?
The load resistor in the NMOS inverter in Figure 16.3(a) is RD = 40 kΩ. The circuit is biased at VDD = 3.3 V. (a) Design the transistor width-to-length ratio such that vO = 0.1 V when vI = 3.3 V. (b) Using the results of part (a), determine the transition point for the transistor. (c) Using the results of part (a), find the maximum current and maximum power dissipation in the inverter.
For the BJT circuit shown Fig. Q7, the bipolar junction transistor (BJT) Q1 has the following parameters: IS = 10-15 A and β = 100. The temperature, T = 300 K. (a) Determine the Thevenin equivalent of the circuit within the dashed line box, as shown in Fig. Q7. (6 marks) (b) Determine the values of VB, VC and Vl, and the operation mode of the BJT Q1.
In this question, using the above listed parameter values and with VDD = 3 V, what is the input voltage when both NMOS and PMOS are in saturation? 3 V 1 V 2 V 1.5 V 2.5 V MOSFET Parameters: Electrically-matched devices Kn = 0.1 mA/V2 Kp = 0.1 mA/V2 VTN = |VTP| = 1 V λn = λp = 0 V-1
Suppose the hole concentration in silicon sample is described mathematically by p(x) = 10^5 + 10^19 exp(-x/Lp) holes/cm3 , x ≥ 0 in which L p is known as the diffusion length for holes and is equal to 2.0 µm. Find the diffusion current density for holes as a function of distance for x ≥ 0 if Dp = 15 cm2/s. What is the diffusion current at x = 0 if the cross-sectional area is 10 µm^2?
Measurement of a circuit incorporating what is thought to be an ideal op amp shows the voltage at the op-amp output to be -2.000 V and that at the negative input to be -1.000 V. For the amplifier to be ideal, what would you expect the voltage at the positive input to be? If the measured voltage at the positive input is -1.005 V, what is likely to be the actual gain of the amplifier?
The enhancement-load transistor in the NMOS inverter in Figure P16.8 has a separate bias applied to the gate. Assume transistor parameters of Kn = 1 mA/V2 for MD, Kn = 0.4 mA/V2 for ML, and VTN = 1 V for both transistors. Using the appropriate logic 0 and logic 1 input voltages, determine VOH and VOL for: (a) VB = 4 V, (b) VB = 5 V, (c) VB = 6 V, and (d) VB = 7 V.
The BJT in the following circuit is a 2N2222 p-n-p BJT. The transistor has the following characteristics: β = 160 VBEon = 0.73 V r0 = 200 kΩ Cμ = 7.3 pF Cπ = 22 pF Analyze the circuit and determine the mid-band gain of the system and the corner frequencies. Verify the analysis with a LTSpice simulation.
In this problem, ideal op amps have the following device parameters all equal to infinity: (A: gain; Ri: Input resistance; Ro: output resistance; IB: Input bias current; los: Offset current; Vos: Offset voltage; CMRR: Common-mode rejection ratio; ft: Unity-gain frequency; f3 dB: 3 dB bandwidth; SR: Slew rate) A, ft, SR, Vos, f3dB A, ft, CMRR, SR A, Ri, los, Vos A, Ro, CMRR, ft A, Ro, IB, los
A 5-µm-long block of p-type silicon has an acceptor doping profile given by NA(x) = 10^14 + 10^18 exp(-10^4x), where x is measured in cm. Use Eq. (2.17) to demonstrate that the material must have a nonzero internal electric field E. What is the value of E at x = 0 and x = 5 µm? (Hint: In thermal equilibrium, the total electron and total hole currents must each be zero.)
Calculate the power dissipated in each inverter circuit in Figure P16.13 for the following input conditions: (a) Inverter a: (i) vI = 0.5 V, (ii) vI = 5 V; (b) Inverter b: (i) vI = 0.25 V, (ii) vI = 4.3 V; (c) Inverter c: (i) vI = 0.03 V, (ii) vI = 5 V.
A BJT (β = 200) is implemented in an amplifier circuit, with a VCC of 15 volts. One wishes to set the Q point at IC = 4.1 mA and VCE = 7.46 volts (DC). Determine the dynamic resistance rd.
What is the maximum possible drain current value for the inverter (this happens when both NMOS and PMOS are in saturation)? VDD = 5 V 0 A 56.25 μA 15.6 μA 31.3 μA 112.5 μA MOSFET Parameters: Electrically-matched devices Kn = Kp = 50 µA/V2 VTN = |VTP| = 1 V λn = λp = 0 V-1
Figure P2.47 gives the electron and hole concentrations in a 2-µm-wide region of silicon. In addition, there is a constant electric field of 25 V/cm present in the sample. What is the total current density at x = 0? What are the individual drift and diffusion components of the hole and electron current densities at x = 1.0 µm? Assume that the electron and hole mobilities are 350 and 150 cm2/V•s, respectively.
Nonideal (i.e., real) operational amplifiers respond to both the differential and common-mode components of their input signals (refer to Fig. 2.4 for signal representation). Thus the output voltage of the op amp can be expressed as vO = AdvId +AcmvIcm where Ad is the differential gain (referred to simply as A in the text) and Acm is the common-mode gain (assumed to be zero in the text). The op amp’s effectiveness in rejecting common-mode signals is measured by its CMRR, defined as CMRR = 20 log|Ad/Acm| Consider an op amp whose internal structure is of the type shown in Fig. E2.3 except for a mismatch ∆Gm between the transconductances of the two channels; that is, Gm1 = Gm – 1/2∆Gm Gm2 = Gm + 1/2∆Gm Find expressions for Ad , Acm, and CMRR. What is the maximum permitted percentage mismatch between the two Gm values if a minimum CMRR of 60 dB is required?
For the two inverters in Figure P16.14, assume (W/L)L = 1 for the load devices and (W/L)D = 10 for the driver devices. (a) If vI is a logic 1, determine the values of vO1 and vO2. (b) Repeat part (a) if vI is a logic 0.
In the amplifier circuit shown below, the BJT transistor has a β = 99 and the base emitter junction of the BJT when it is forward biased has a voltage drop of 0.7 V, i.e., VBE = 0.7 V. Consider that all three external capacitors shown in this circuit have very large values. Determine the DC values of the parameters shown in the Table below.
In this question, choose values for R2 and R1 in the above circuit so that output signal is an undistorted sine wave of 10 volts peak amplitude. The op amp is characterized by the device parameters listed to the right of the circuit. R2, R1 values: 20 Ω, 1 Ω 400 Ω, 10 Ω 2 kΩ, 50 Ω 40 Ω, 1Ω 1 kΩ, 50 Ω Op-amp Parameters: vOMAX = ±23 V iOMAX = ±10 mA ft = 5MHz SR = 10 V/μs
A diode is doped with NA = 10^18/cm3 on the p-type side and ND = 10^19/cm3 on the n-type side. (a) What is the depletion-layer width wdo? (b) What are the values of x p and xn? (c) What is the value of the built-in potential of the junction? (d) What is the value of EMAX? Use Eq. (3.3) and Fig. 3.5.
Assuming ideal op amps, find the voltage gain vo/vi and input resistance Rin of each of the circuits in Fig. P2.8.
Consider the circuit in Figure P16.15. The parameters of the driver transistors are VTND = 0.8 V and (W/L)D = 4, and those of the load transistors are VTNL = -1.2 V and (W/L)L = 1. (a) If vI is a logic 1, determine the values of vO1 and vO2. (b) Repeat part (a) if vI is a logic 0.
Consider the BJT based current amplifier shown here. In the circuit shown, iout is measured as 8.3 mA when a load is connected. Given that hfe = 60, determine the value of iin. (Assume the transistor is not saturated.)
In this question, ideal op amps have the following device parameters all equal to zero: (A: gain; Ri: Input resistance; Ro: output resistance; IB: Input bias current; los: Offset current; Vos: Offset voltage; CMRR: Common-mode rejection ratio; ft: Unity-gain frequency; {3 dB: 3 dB bandwidth; SR: Slew rate) IB, los, Vos, Ri los, Vos, Ro Ri, Ro, Vos ft, SR, CMRR ft, SR, Ro
The maximum velocity of carriers in silicon is approximately 10^7 cm/s. (a) What is the maximum drift current density that can be supported in a region of p-type silicon with a doping of 5 × 10^17/cm3? (b) Repeat for a region of n-type silicon with a doping of 4 × 10^15/cm3?
A particular inverting circuit uses an ideal op amp and two 10-kΩ resistors. What closed-loop gain would you expect? If a dc voltage of +1.00 V is applied at the input, what outputs result? If the 10-kΩ resistors are said to be “1% resistors,” having values somewhere in the range (1 ± 0.01) times the nominal value, what range of outputs would you expect to actually measure for an input of precisely 1.00 V?
For the saturated load inverter shown in Figure 16.9(a), assume transistor parameters of VTNDO = VTNLO = 0.5 V, KD = 200 μA/V2, KL = 20 μA/V2, γ = 0.25 V1/2, and φfp = 0.35 V. Determine vO for vI = 0.12 V for the case when (a) the body effect is neglected and (b) the body effect is taken into account. Consider the NMOS inverter with depletion load in Figure 16.9(b). The transistor parameters are VTNDO = 0.4 V, VTNLO = -0.6 V, K D = 100 μA/V2, KL = 20 μA/V2, γ = 0.25 V1/2, and φfp = 0.35 V. Determine vI when vO = 1.25 V for the case when (a) the body effect is neglected and (b) the body effect is taken into account.
The BJT transistor in the amplifier circuit shown below has a beta equal to 100 and a base emitter voltage drop of 0.7 V when this junction is forward biased. The resistance RL is 10 kΩ The small signal source provides a sine wave with zero average. a) Find the value of resistance RE to establish a DC emitter current of 0.2 mA. b) Find the value of resistance RC to establish a DC collector voltage of +0.5 V. c) Using the hybrid-π model for this transistor draw the equivalent amplifier circuit under small signal conditions and calculate the voltage gain of this amplifier: Av = vo/vsig
Suppose that NA(x) = No exp(-x/L) in a region of silicon extending from x = 0 to x = 8 µm, where No is a constant. Assume that p(x) = NA(x). Assuming that jp must be zero in thermal equilibrium, show that a built-in electric field must exist and find its value for L = 1 µm and No = 10^18/cm3.
Consider the circuit with a depletion load device shown in Figure P16.18. (a) For vX = 1.8 V and vY = 0.1 V, determine KD/KL such that vO = 0.1 V. (b) Using the results of part (a), determine vO when vX = vY = 1.8 V. (c) If the width-to-length ratio of the depletion load is (W/L)L = 1, determine the power dissipation in the logic circuit for the input conditions listed in parts (a) and (b).
If the circuit's input voltage changes to VI = 0.1sin(ωt) V, assuming that the op amp is an ideal device, solve for its output current io. 2 sin(ωt) mA 0.2 sin(ωt) mA 1.1 sin(ωt) mA 2.2 sin(ωt) mA 1 sin(ωt) mA
Consider the three-input NOR logic gate in Figure P16.19. The transistor parameters are VTNL = -1 V and VTND = 0.5 V. The maximum value of vO in its low state is to be 0.1 V. (a) Determine KD/KL . (b) The maximum power dissipation in the NOR logic gate is to be 0.1 mW. Determine the width-to-length ratios of the transistors. (c) Determine vO when vX = vY = vZ = 3 V.
For the BJT cascaded voltage amplifier shown in Fig. 3, Assume that the two transistors are identical with the following parameters: VBE = 0.7 V, β = 100, VA = ∞, Calculate: The DC collector currents for Q1 and Q2 The mid-band voltage gain (Vout /Vin) The second stage input resistance Rin2
In this question, the circuit’s input voltage is V1 = 0.02sin(ωt) V. Assuming that the op amp is an ideal device, solve for its output voltage VO. 2sin(ωt)V 0.1sin(ωt)V 10sin(ωt)V 1sin(ωt)V 20sin(ωt)V
In this problem, if we require the op amp's output voltage to be 1.0sin(ωt) ∨ without being slew-rate limited for frequencies up to 200 kHz, choose the minimum value from the following list of possible slew rates that will satisfy this specification. 0.01 V/μs 1 V/μs 1.5 V/μs 2 V/μs 0.1 V/μs
For the current-mirror-loaded BJT differential amplifier in Figure 1, let I = 0.6 mA, VA = 120 V, and β = 120. Find differential gain Ad = vo/vid and differential input resistance Rid. vid = vB1 - vB2
The BJT transistor in the circuit shown below has a β = 100 and a base emitter voltage drop of 0.7 V when the base emitter diode is forward biased. Each of the two diodes, D1 and D2, can be modelled with a constant voltage drop of 0.7 V when forward biased and as an open circuit when reversed biased. Determine the value of the currents ID1 and ID2, that flow through these two diodes.
Consider the npn BJT amplifier circuit in the below figure. Assume that the source provides a small signal vsig and the BJT has β = 100. Neglect Early effect (ro). VT = 25 mV. Assume IB ≈ 0 or IE ≈ IC (or α ≈ 1 ). (a) Draw the small-signal equivalent circuit. Use the T-equivalent model (αi -version) to replace the BJT. (b) Determine the overall voltage gain (vo/vsig).
For the basic/reference inverter with n = (W/L)n = 1.5 and p = (W/L)p = 3, find the proper W/L for transistor Q1 and Q4. W/L for Q1, Q4: O 3, 3 6, 1.5 3, 1.5 6, 6 6, 3 If the basic/reference inverter with n = (W/L)n = 1.5 and p = (W/L) = 3. Find the proper W/L for transistors Q1 and Q4
In the circuit shown, V1 = 0 and V2 = Vdd. The other relevant parameters are mentioned in the figure. Ignoring the effect of channel length modulation and the body effect, the value of Iout is mA (rounded off to one decimal place).
The CG amplifier shown below is biased by I1 = 1 mA. Assume λ = 0 and C1 is very large. (a) What value of RD places the transistor M1 150 mV away from the triode region? (b) What is the required W/L if the circuit must provide a voltage gain of 6 with the value of RD obtained in (a)?
In the circuit above, the MOSFET and BJT have the following parameters, K = 4 mA/V2, VT = 0.9 v, β = 100, VBE( active) = 0.7 v, VBE (sat) = 0.8 v (a) Find out the gate voltage of the MOSFET. (b) Calculate V1. (c) Find out the expression for VGS, VDS and VOV. (d) Find the operating mode of the MOSFET using the expressions from (C). [Hint: You don't need any assumption] (e) Calculate IDS and VDS using the given parameters. (f) Assume that the BJT is in the saturation mode. Now, calculate IB, IC, IE. You must validate the given assumption.
Consider the NMOS inverter with depletion load in Figure 16.7(a). Let VDD = 1.8 V, and assume VTND = 0.3 V and VTNL = -0.6 V. (a) Design the circuit such that the power dissipation is 80μW and the output voltage is vO = 0.06 V when vI is a logic 1. (b) Using the results of part (a), determine the transition points for the driver and load transistors. (c) If (W/L)D found in part (a) is doubled, what is the maximum power dissipation in the inverter and what is vO when vI is a logic 1? The NMOS inverter with depletion load is shown in Figure 16.7(a). The bias is VDD = 2.5 V. The transistor parameters are VTND = 0.5 V and VTNL = -1 V. The width-to-length ratio of the load device is W/L = 1. (a) Design the driver transistor such that vO = 0.05 V when the input is a logic 1. (b) What is the power dissipated in the circuit when vI = 2.5 V?
Determine the sizes of the NMOS and PMOS devices so that the network has approximately the same worst case tpHL and tpLH as an inverter (with an NMOS W/L = 1µm/0.25µm and PMOS W/L = 2µm/0.25µm.) which is driving an external capacitance of 20pF. Avoid increasing the area unnecessarily.