The circuit shown below is a differential amplifier with a 2nd stage amplifier. IBias is an MOS transistor-based current source (a current mirror, for example). Describe the function of each of the transistors.
The circuit shown in Fig. P4.1-2 illustrates a single-channel MOS resistor with a W/L of 2 µm/1 µm. Using Table 3.1-2 model parameters, calculate the small-signal ON resistance of the MOS transistor at various values for VS and fill in the table below. VS (volts) R (ohms) 1.0 3.0 5.0
The circuit in the figure to the right is a current mirror. The supply voltages are ±6 V. The two transistors are equivalent and have VBE = 0.7 V, VCE,sat = 0.3 V, VA = 80 V, and β = 200. The reference resistor is RREF = 11 kΩ. Calculate the collector current of transistor Q1, IC,Q1.
Derive the output resistance of the current mirror shown in Fig. P3.19 where a diode-connected transistor has been included in series with the source of the output transistor. Ignore the body effect. Fig. P3.19
Figure 1 shows a folded-current mirror differential amplifier implemented in 18 nm finFET technology. Assume VDD = 1 V, Iref = 25 µA, nfinp = 150 for the pMOS, and nfinn = 100 for the nMOS transistors. a) Find the maximum input common-mode voltage, VIC(max), and the minimum input common-mode voltage, Vic(min). Assume all transistors are in saturation. b) What is the input common-mode voltage range, ICMR? c) Find the small-signal differential voltage gain, Avd = Vout/ (Vin+ - Vin-). d) If a 10pF capacitor is connected between the output and ground, what is the -3 dB frequency of Avd(jω) in Hz ? Neglect any device parasitic capacitance.
Shown in Fig. P3.22 is a PMOS current mirror with VDD = 1.8 V, Ibias = 150 µA, R = 2 kΩ, and all transistors sized (W/L) = 18 µm/0.2 µm and having the device parameters for the 0.18-µm CMOS process in Table 1.5. a. With v0 = 1 V, are all transistors in active mode? b. What is the maximum voltage that can appear at vo while still keeping all transistors in active mode? c. Assuming all transistors are in active mode, what is the small-signal output resistance seen looking into the drain of Q4? d. Compare this current mirror to the conventional cascode current mirror presented in Section 3.6.
A NMOS cascode amplifier with active load is shown in Fig. P3.23. It is realized using the 0.35-µm CMOS devices in Table 1.5 with VDD = 3.3 V, Ibias = 100 µA, (W/L)1,2,5,6 = 10 µm/0.5 µm, and (W/L)3,4 = 30 µm/0.5 µm. a. Estimate the small-signal gain, vo/vi , and output resistance. b. What is the total power consumption of the circuit? c. Estimate the range of output voltages over which all transistors will remain in active mode. Modify the design of Problem 3.23 in order to double its small-signal gain without changing its power consumption Fig. P3.23
Calculate the output resistance and the minimum output voltage, while maintaining all devices in saturation, for the circuit shown in Fig. P4.3-4. Assume that iOUT is actually 10 µA. Simulate this circuit using SPICE LEVEL 3 model (Table 3.4-1) and determine the actual output current, iOUT and small-signal output resistance, rOUT. Use Table 3.1-2 for device model information.
To improve the performance of the differential amplifier shown in Figure Q1, the biasing current source is replaced by a Widlar current source. The collector resistors are replaced by a current mirror formed by the matched bipolar transistors Qs and Q6, and the bipolar transistors Q1 and Q2 are replaced by the matched field-effect transistors M1 and M2. A single-sided output at the drain terminal of M2 is used. The transistor parameters for the bipolar transistors are: β = 100, VBE (on) = VEB(on) = 0.7 V, and VA = 100 V. The transistor parameters for M1 and M2 are: Kn = 0.15 mA/V2, VT N = 0.8 V, λ = 0.01 V-1 . The improved differential amplifier is shown in Figure Q2. (a) Determine the quiescent voltages and currents of M1 and M2 when v1 = v2 = 0. (4 marks) (b) Design the value of resistor RE such that IQ = 0.1 mA. (2 marks) (c) Determine the maximum and minimum common-mode voltages that can be applied to v1 and v2. (3 marks) (d) Determine the percentage change in IQ when the common-mode voltage applied to v1 and v2 changes from the maximum to the minimum value obtained in part (c). (5 marks) (c) Define vd = v1 - v2, determine the differential-mode voltage gain Ad of the improved differential amplifier.
(a) Calculate the small - signal voltage gain of the circuit below. (b) Pspice simulation: Take VDD = 5V, RL = 10kΩ. Plot Vout Vs. Vin from 1V to 3V. Calculate the voltage gain. (Use provided NMOS and PMOS model) (c) In - lab: Take VDD = 5 V, RL = 10kΩ., build the current mirror, plot Vout vs. time at Vin = 1 V, 1.5 V, 2 V and 2.5 V. Use these Vout data you got in lab, plot Vout vs. Vin curve on your own.
Calculate the effect of charge injection on the circuit shown in Fig. P4.1-13. Assume that U = 5 V/50 ns = 10^8 V/s and vin = 2.5 V and ignore the bulk effect. Use the model parameters from Tables 3.1-2 and 3.2-1.
Given the circuits on the left. Ignore the channel length modulation. Assume these transistors are fabricated on the same technology such that all NMOS transistors have the same Vt,n and µn, and all PMOS transistors have the same Vt,p and µp. Prove that if all transistors are in saturation, the following relationships between the transistor currents are true: ID2/ID1 = (W/L)2/(W/L)1 and ID4/ID3 = (W/L)4/(W/L)3.
In a particular cascaded current mirror circuit, the transistors have VT = 0.6 V, µnCox = 160 µA/V2, L = 1 µm, VA = 10 V. The widths for Q1, Q4, Q3 and Q2 are W1 = W4 = 4 µm and W2 = W3 = 40 µm, respectively. The reference current is IREF = 20 µA. What is the value of output current I0? What are the voltages at the gates of Q2 and Q3? What is the lowest voltage at the output for which current possible? What are the values of gm and r0 of Q2 and Q3? (Note: early effect is present) Draw the small signal ac mode for this circuit with the hint that for diode connected transistors act as a wire in the ac-analysis. What is the value of VGS2?
Consider the MOSFET current mirror shown below. For these transistors, kn’ = 0.2 mA/V2, VTn = 0.5 V. Unless expressly stated, you may assume that λ = 0 throughout the analysis. For M1, (W/L)1 = 2 and IREF = 0.2 mA. We wish to achieve ID2 = 1 mA and ID3 = 2 mA. a) What value of (W/L)2 is required? b) What is the minimum allowable value of VD2? c) What value of (W/L)3 is required? d) What is the minimum allowable value of VD3? e) Consider the min VD2 value determined in part b). Suppose that we include the effect of λ in the DC ID - VGS expression (with λ = 0.01). What value of ID2 would you expect for this output voltage point? Your calculations can consider only M2. f) Suppose that VDD = 7 V and that the "Amp Circuit" connected to M2 can operate at VD2 values up to 6 V. We include the effect of λ in the DCID - VGS expression (with λ = 0.01). What value of ID2 would you expect for this maximum output voltage point? Your calculations can consider only M2.