For the given circuit Vin1 = Vin2 = 0 V, Vout1 = Vout2 = 0.1 V. All transistors operate at Vov = 0.15 V and assume that Vth,n = 0.4 V and µnCox = 400 µA/V2, λ = 0.2 V-1 . a. Find the values of R, RD1 = RD2 = RD, and the W/L ratios of all transistors. Let’s consider a 10% increase in RD1 while keeping RD2 unchanged. b. Find the differential-mode gain (ADM) = (Vout1 - Vout2 / Vin1 - Vin2) and common-mode gain (ACM-DM) = (Vout1 - Vout2/Vcm). c. What is the input common-mode voltage range?
(CMOS Logic Gate Design - 10 points) Recall that CMOS logic gates consist of a pull-down and a pull-up network comprising of NMOS and PMOS transistors, respectively. Moreover, CMOS gates implement inverting logic. Keeping this in mind, design a CMOS gate that implements the following Boolean expressions. Note that you are asked to design just one logic gate implementing the entire Boolean function. Use as few transistors as possible. Make sure to label the input (gate of each transistor) variables accordingly. Furthermore, don’t forget to show where the output of the logic gate is. a) X • Y + Z b) A • B + C • D c) A¯ + B¯ + C¯ d) (A¯ + B¯) • (C¯ + D¯)
3. Design a common-source amplifier with a diode-connected load based on the schematic shown below with the following design specifications: • Transistor M1 is in saturation • The minimum possible output voltage to keep M1 in saturation is 0.25 V • Total power consumption of the amplifier is 3 mW • Both transistors have L = 0.5µm • DC level of the output is 1.5 V The technology parameters are: λ(NMOS) = 0, γ = 0, VDD = 3 V, VTH(NMOS) = 0.5 V, µnCox = 1 mA/V 2 Find the following values: a) Width of the transistors, i.e., W1 and W2 [5 marks], b) DC level of the input [5 marks], d) Small-signal gain [5 marks]. e) Maximum symmetric output signal swing while both transistors stay in saturation [ 5 marks].
Consider the following amplifier circuit. Both MOSFET’s have the following specifications: (W/L) = (6µm/0.18µm), processing parameters kp = µpCox = 70µA/V2 , kn = µnCox = 270µA/V2 , |Vt| = 0.45 V, V Ω A = 12.5 V/µm = VA, and Q1 is biased so that Vov = 200mV, gate of Q2 is at DC voltage VG = 0.96 V and VDD = 1.8 V. a. What is the configuration of amplifier, i.e. CE or CB or CD or CS or CG or CC or CD or CS with active load or CG with active load or CE with active load or CB with active load or CD with active load or CC with active load or CE using 0.18µm technology? Or none of the above the correct answer is b. Find the small-signal output resistance Rout and input resistance Rin looking into gate Q1 c. Calculate small-signal voltage gain of the amplifier Av = [vo/vi ] d. What is the voltage swing at the output, i.e. vomax and vomin ? e. Calculate the power consumed by the amplifier.
A CMOS circuit is shown in Fig. P9.5. Suppose that the precharge transistor was chosen such that node X is guaranteed to be charged to VDD. All nMOS transistors have W/L = 20. Determine how long it takes for the node voltage at X to decrease to 0.8VDD after the clock signal pulse goes to high (with zero rise time) when input voltages at A, B, D are 1.2 V and the input voltage at C is zero. Assume the following parameter values: γ = 0.0 V1/2 • VT0 = 0.48 V • k 0 n = 102µA/V2 a Ec,nLn = 0.4 Hint: The nMOS transistor tree between node X and the ground can be approximated by an equivalent transistor with an effective W/L. Hint 2: You need to solve a super easy integral.
For the CMOS circuit below, what is the voltage labeled V0? -5 V -4.1 V -0.9 V +0.9 V +4.1 V +5 V Vtn = |Vtp| = 0.9 V
In the given common-base amplifier circuit below, the voltage source VB is a constant voltage source that, along with the DC component of the input voltage, sets the quiescent collector current of the PNP transistor at 1 mA. The transistor has β = 150, ro → ∞, Cπ = 10pF, and Cµ = 2pF. The amplifier is fed with an input source having Rin = 5kΩ and has a load resistance RL = 20kΩ. Ignore the capacitance CL and use VT = 25mV. Derive the transfer function and answer the questions below. What is the DC gain? dB What is the frequency of the dominant pole? ωp1 = M rad/sec What is the frequency of the non-dominant pole? ωp2 = G rad/sec
Consider the diode circuit shown in Fig. Q6. Assume VD0 = 0.7 V and the diode breakdown voltage is at 10 V. Fig. Q6 (a) If V1 operates between 0 to 9 V and VDD is 9 V, which operating region would both diodes be in? (b) Supposed R1 is 10kΩ, VDD is 1 V, and V1 is now 20 V. Assume Dl is forward biased and D2 is reversed biased. Determine V2 and thus IR1. (c) Explain why in part (b), the diode D2 is not operating in the breakdown region. (d) Supposed R1 is 10kΩ, VDD is 1 V, and V1 is now -20 V. Assume D2 is forward biased and D1 is reversed biased. Determine V2 and thus IR1.
Part 1: Hand Calculation Consider the following circuit with the following parameters: • Load: is a depletion NMOS, VT(load) = -1 V, kn0 = 100uA/V2 ,( W/L)Load = 6 • Driver: is an enhancement NMOS with VT(driver) = 0.5 V, kn0 = 100uA/V2 ,( W/L)driver = 4 • VDD = 3 V Neglect body effect and calculate: a) vO for vI = 0 V and vI = 1 V b) vo for vI = 2 V and vI = 3 V c) The transition point for the load transistor d) The transition point for the driver transistor e) The point where vO = vI f) Sketch the voltage transfer characteristics (VTC) indicating the points calculated before Part 2: Simulation Draw the circuit on LTSpice and use the part nmos 4 connecting its body terminal to its source, with parameters as in Part 1 (note that in LTSpice, the parameter kn’ is called kp and the parameter VT is called VTO, and you can set W/L by right clicking on the transistor). a) Draw the VTC, and Verify the results of part 1 b) Repeat the simulation with (W/L)driver = 8, • find the point where vO = vI from the VTC • how does increasing (W/L) driver of the affect the VTC ? Notes: • Homework submission is through the Moodle platform • Submit a single compressed file containing: • The hand calculations • Screenshot showing the circuit and the simulation results • The schematic file (.asc) • The netlist file (.net)