Consider the following NMOS gate in Fig. 1. A) Write the logic function for this logic gate B) Find the ideal output if : VA = 0 V, VB = 0 V, VC = 0 V, VD = 0 V and VDD = 5 V C) Find the ideal output if : VA = 5 V, VB = 0 V, VC = 5 V, VD = 0 V and VDD = 5 V Fig. 1. D) Find the Practical output if: VA = 5 V, VB = 5 V, VC = 0 V, VD = 0 V, VOL = 0.7 V and VDD = 5 V E) Find the Practical output if : VA = 5 V, VB = 5 V, VC = 5 V, VD = 5 V, VOL = 0.7 V and VDD = 5 V
Replace the circuit with its small-signal model, and use the test signal method to obtain an expression for Rds. Calculate Rds, if R1 = R2 = 1 MΩ, and the PMOS has gm = 1 mS and ro = 100 kΩ.
6. Fig. 6 shows a cascode current mirror. Assume that (W/L)M1 = (W/L)M2 = (W/L)M3 = n1•(W/L)M4, IREF = 20 µA.Vtn = 0.7 V for all transistors and |Vov| = 0.2 V for all transistors except M4. (a) To design IOUT = IREF without considering channel-length modulation, please calculate n1 to minimize the allowable output voltage Vout while all transistors work in saturation region. (b) Find the minimum allowable VOUT as mentioned in (a). (c) If the channel-length modulation λn = 0.05 V-1 is considered, please calculate the IOUT when VOUT is biased at its minimum value. (d) Draw a modified circuit to cancel the error due to channel length modulation. Explain your reason. (Hint: the wide-swing current mirror shown in the textbook is one solution.) Fig. 6
(Equivalent Resistance and RC time constant) In the following circuit, the capacitor CL = 726 fF is initially charged to VDD = 2.5 V before Vin switches to zero as shown in the figure bellow. The threshold voltage of PMOS, VTP = -0.9 V. If we replace M1 with a resistor R = 12 KΩ when conducting, a) How long does it take for the capacitor to discharge to VDD/2 ? b) What is the final voltage on the capacitor? How long does it take for the capacitor to get to this final voltage? c) Sketch the voltage across CL as a function of time. Assume no leakage current exists. d) Using no more than three sentences, and/or a sketch, indicate the main difference(s) between the voltage as a function of time curve for the resistor-switch model and a real PMOS.