(a) Using quantitative analysis, derive the voltage gain of differential pair, assuming the circuit to be symmetric and both transistors M1 and M2 are saturated. (b) In the circuit shown in Fig. 2, (W/L)1,4 = 50/0.5 and ISS = 1 mA : Fig. 2 (i) What is the small-signal differential gain? (ii) For Vin, CM = 1.5 V, what is the maximum allowable output voltage swing?
A transistor schematic diagram of a digital circuit is shown below (Fig. 3.1). The sizes of the MOS transistors are given as ratio (W/L)n = 4 and (W/L)p = 2. |It is also given that |VTn| = VTp = 0.5 V and µnCox = 10-4 A/V2 while µpCox = 5 × 10-5 A/V2 . Fig. 3.1 (a). Draw the logic gate symbol of the above CMOS digital circuit. (2 marks) (b). Sketch the output waveform Vout for the given input voltage signals VA and VB. Assume that the logic circuit is fast enough to respond to the given input waveform. Voltage levels and any other key features must be labelled properly. (8 marks) (c). If both the inputs VA and VB are connected to VDD, determine the equivalent resistance linking the output to ground. (7 marks) (e). If the inputs VA and VB are tied together, sketch a graph of the output voltage Vout as a function of VA from 0 V to 1.8 V in the static case. Any turning point(s) or important features (e.g. voltage levels) as well as axes must be shown clearly or labelled explicitly. (8 marks)
17.8 Consider the MOSFET of Problem 17.2 to be used in the inverter circuit of Figure P17.7. Graphically determine the VTC for the inverter circuit for VT ≤ VIN ≤ VDD. FIGURE P17.7
[Small Signal Analysis] Consider the following amplifier circuit consisting of an N-type MOSFET, λ = 0 and vSB = 0. RG = 100kΩ, RD = 3kΩ, RS = 1kΩ, CC and CS are both so large that 1/(jωC) ∼ 0 at the frequency of interest. VDD = 1.0v. The MOSFET has kn = 0.8 mA/V2 and Vt = 0.4v. (a) Analyze the DC bias point of this circuit. What are the DC values of VOUT and VS , respectively? (b) Calculate gm for the MOSFET. (c) What is the maximum allowed value of RD so that the MOS transistor remains in saturation mode? (d) Draw the small signal equivalent circuit for this amplifier. (e) What is the small signal gain Av? (f) What is the input resistance Rin?
[MOSFET Circuits] Consider the MOSFET circuit as shown below. R = 1kΩ, kn’ = 1 mA/V2 and Vtn = 0.3 V for both Q1 and Q2, W/L = 0.5μm/0.1μm for Q1, W/L = 1μm/0.1μm for Q2, λ = 0 and vSB = 0. (a) Calculate the voltage at the drain terminal of Q1. (b) What is the ratio of iD1 to iD2, where iD1 is the drain current for Q1 and iD2 is the drain current for Q2. Hint: This circuit is called the "current mirror" circuit, where the ratio of iD1 to iD2 is a fixed number, determined by W1, W2, L1 and L2, as long as both transistors are biased in saturation mode. (c) What is the maximum value of R2 so that Q2 remains in saturation mode?
Fig. 3 as follows is an IC layout of a CMOS implementation of a two-input digital logic gate. The truth table of the logic gate is also given. Vin1 Vin2 Vout 0 V 0 V 3 V 0 V 3 V 3 V 3 V 0 V 3 V 3 V 3 V 0 V Fig. 3 (a). How many MOSFETs are there in the IC layout shown above? (b). The given layout is drawn according to the lambda (λ) design rules. If λ = 0.15µm and the minimum feature size in the IC layout is 2λ, by examining the given layout or otherwise, determine the width in µm of the MOSFET with the largest transistor size (i.e. W/L). (c). Using the given layout and your answer in (b), hence or otherwise, sketch the transistor schematic diagram of the two-input digital logic circuit. The MOSFETs must be labelled clearly with the transistor size corresponding to the layout (assuming λ = 0.15 µm). (d). If the two inputs are tied together (i.e. Vin1 = Vin2 ), sketch the real DC voltage transfer characteristics (Vout vs. Vin ) of the CMOS digital logic circuit. Assume a supply voltage VDD = 3.0 V and the magnitude of the threshold voltage |Vth| = 0.5 V for the MOSFETs. All key features of the curve as well as the axes must be clearly labelled.
Question: (MOSFET Amplifier) Consider the given MOSFET amplifier circuit and solve the following questions by showing all the solution steps clearly. (Use appropriate component models according to the given parameters). (µn•Cox = 100µA/V2 , W/L = 9/0.18, Vt = 1 V ) a) (30p) Draw the small signal model of the amplifier circuit. Find the input impedance Rin. b) (40p) We want to get a voltage gain Av = -10 with a Q-Point (Id=10mA). Calculate the values of Rd, VGS, VDS and check the operating mode of the MOSFET. c) (30p) Calculate the maximum voltage gain |Av| that can be obtained from this amplifier with a Q-Point (Id=10mA) gm = 2µnCoxW/LIDS IDS = µnCox W/L(VGS - Vt – VDS/2)•VDS, IDS = 1/2 µnCox W/L (VGS - Vt)^2
Consider the differential pair shown in Fig. 1. The power supply voltage is VDD 5 V, and all transistors have μnCox = 100 μA/V2, W/L = 2 and Vt = 1 V. You may neglect channel length modulation (VA = 1). (a) What is the value of VGS for M1 and M2 when no differential input voltage is applied and both transistors are in saturation? (b) What is maximum common mode input voltage (hint: all transistors must remain in saturation for normal operation)?
In the following feedback amplifier, assume that M1, M2, and M3 are all biased to be in the saturation region. Consider λ = 0 (30 points). a. Find the polarity of the feedback. b. Identify the type of feedback. c. Derive the expression for the open-loop voltage gain (AV,OL = Vout /Vin ), including the loading effects of the feedback. d. Determine the value of the feedback factor K and derive the expression for the closed-loop voltage gain (Av,CL = Vout/Vin). e. Derive the expression for the closed-loop output resistance Rout,CL.
Consider the CMOS complex gate on the right, for which the nMOS network (n-net) is represented with a box. a) Complete the CMOS gate circuit by drawing the nMOS transistors (i.e. inside of the corresponding n-net) as well. b) Express the Boolean logic function realized by this complex CMOS gate. c) By removing some transistors from the circuit in (b), we want to realize a simpler function of Z = (J + KL + ML)’. Draw the new simpler circuit. Please also explain why/how you removed which transistors and why/how you replaced which input signals with the new J, K, L, M input signals.