Enhancement-mode NMOS and PMOS devices both have parameters L = 4 µm and tox = 500 A0 . For the NMOS transistor, VTN = 0.6 V, µn = 675 cm2/V - s, and the channel width is Wn for the PMOS transistor, VTP = -0.6 V, µP = 375 cm2/V -s, and the channel width is WP. Design the widths of the two transistors such that they are electrically equivalent and the drain current in the PMOS transistor is ID = 0.8 mA when it is biased in the saturation region at VSG = 5 V. What are the values of Kn, KP, Wn, and WP?
For the depletion type MOSFET amplifier circuit shown in Fig. Q.1, Figure Q. 1 i. Draw the small ac signal equivalent circuit. Neglect r0. ii. Calculate ID, Zi, ZO, and AV . Vov = VGS - VTh. iii. Calculate the coupling and bypass capacitors so that the low cutoff frequencies are fc1 = fc2 = 10 Hz, and fcs = 100 Hz. What is the low cutoff frequency (fL) of the amplifier?
Consider the amplifier circuit in Fig. 4. Assume the channel-length modulation effect of Q1 and Q2 is negligible. (a) Assume all transistor operate in the saturation region. Which action(s) below would cause the voltage gain vo/vi to increase? (i) Increase VG1 (ii) Increase VG2 (iii) Increase RD? Please explain your answer clearly. (9%) (b) Which action(s) below could cause Q1 to leave saturation operation (i.e. entering triode operation) (i) Increase VG1 (ii) Reduce VG2 (iii) Reduce RD? Please explain your answer clearly. (9%) (c) If Q2 is found to operate in triode region, please suggest how each parameter below should be adjusted (increased or decreased) to bias Q2 in saturation region again? (i) VG1 (ii) VG2 (iii) RD. Please explain your answer clearly. (9%) Figure 4
Two CMOS inverters are connected together as shown below (Fig. 2.1). If it is needed in calculations, please use the following assumed data: gate oxide thickness tox = 7.6 nm for silicon dioxide (SiO2); built-in voltage Vbi = 0.7 V; zero-bias bottom-area junction capacitance (normalised) Cj0An = 1.10×10-4 F/m2; zero-bias sidewall capacitance ( normalised) Cj0swn = 2.19×10-11 F/m; state your assumption clearly if other additional data are needed. Sizes of M1 to M4 : (W/L)n = 0.4μm/0.2μm (W/L)p = 1.0μm/0.2μm (a). With the input waveform shown in Fig. 2.1, at time t1, what are the expected operation modes of the two n-type MOSFETs respectively? Assume that the inverters are fast enough to respond to the given input waveform. (5 marks) (b). Determine the dominant drain capacitance of M2 at time t1. Assume the worst case of the sidewall capacitance contributed from four sides. (10 marks) (c). Determine the dominant gate capacitance of M3 at time t1. (Hint: the bulk terminal of each of the MPSFET is connected to either ground or VDD ). ( 6 marks) (d). Draw a sketch comparing the output waveform with the input signal, taking into account the qualitative effects of capacitance within the MOS transistors. (4 marks)
Consider the CMOS Circuit shown below. The MOSFET parameters are kn’ = 3kp’ = 0.3 mA/V2, and VT = 0.7 V, and RX = 1 kΩ. a) Find the drain current ID = Correct Answer: .25 mA b) The region of operation of the NMOS transistor is Correct Answer: Triode, Linear c) The region of operation of the PMOS transistor is Correct Answer: Active, Saturation