The input to an inverting opamp amplifier circuit (as shown in Figure 4.11 in our textbook) is v s = −0.1 V and Rs = 1kΩ. If the opamp's supply voltage is Vcc = 10 V, what is the maximum value that Rf can assume before saturating the op amp? Figure P4.11: Circuit for Problems 4.11 and 4.12.
Assume the following unless stated otherwise for a 0.25 μm CMOS process: VDD = 5 V, Lmin = 0.25 μm Vtn = 0.5 V or −1 V (choose accordingly), Vtp = −0.5 V μnCox = 265 μA/V2, μpCox = 90 μA/V2 Consider a resistively loaded inverter with a load of Ctot = 300 fF. a) Design the inverter (specify W, L values for the transistor, and RL) so that VOL = 0.025 V. b) Calculate all the other voltages of the voltage transfer characteristic. c) Find the noise margins and the area of the inverter.
Assume the following unless stated otherwise for a 0.18 μm CMOS process: VDD = 3.3 V, Lmin = 0.18 μm Vtn = 0.5 V or −1 V (choose accordingly), Vtp = −0.5 V μnCox = 390 μA/V2, μpCox = 90 μA/V2 Consider a resistively loaded inverter with a load of Ctot = 180 fF. a) Calculate RL so that VOL = 0.15 V using a minimum-size driver. c) Calculate the τPHL propagation delay using the differential equation method and the RC method. Compare and comment on your results.
Assume the following unless stated otherwise for a 0.18 μm CMOS process: VDD = 3.3 V, Lmin = 0.18 μm Vtn = 0.5 V or −1 V (choose accordingly), Vtp = −0.5 V μnCox = 390 μA/V2, μpCox = 90 μA/V2 Consider a CMOS inverter with a load of Ctot = 250 fF. a) Calculate all five voltages of the voltage transfer characteristic for kn = kp. b) Find the noise margins and the area of the inverter. c) Make a qualitative evaluation of the inverter regarding its static performance. d) Calculate the rise time τr using the RC method
Figure below shows an ideal voltage amplifier with a gain of +2 V/V (usually implemented with an op amp connected in the noninverting configuration) and a resistance R connected between output and input. a) Using Miller's theorem, show that the input resistance Rin = −R . b) Use Norton's theorem to replace Vsig, Rsig, and R in with a signal current source and an equivalent parallel resistance. Show that by selecting Rsig = R, the equivalent parallel resistance becomes infinite and the current IL into the load impedance ZL becomes Vsig/R. The circuit then functions as an ideal voltage-controlled current source with an output current IL. c) If ZL is a capacitor C, find the transfer function Vo/Vsig and show it is that of an ideal noninverting integrator.
Question 4 (P4.57) A source-follower circuit with a saturated load is shown. The transistor parameters are VTND = 1 V, KnD = 1 mA/V2 for MD, and VTNL = 1 V, KnL = 0,1 mA/V2 for ML. Assume λ = 0 for both transistors. Let VDD = 9 V. a) Determine VGG such that the quiescent value of vDSL is 4 V . b) Show that the small-signal open-circuit (RL = ∞) voltage gain about this Q-point is given by Av = 1 1 + KnL/KnD. c) Calculate the small-signal voltage gain for RL = 4 kΩ.
9.14. (a) Draw the low-frequency ac and midband equivalent circuits for the common-base amplifier in Fig.P9.14. if Rl = 75 Ω, RE = 4.3 kΩ, RC = 2.2 kΩ, R3 = 51 kΩ, and β0 = 100. (b) Write an expression for the transfer function of the amplifier and identify the location of the two low-frequency poles and two low-frequency zeros. Assume r0 = ∞ and the Q-point = (1.5 mA, 5 V). (c) What are the midband gain and lower cutoff frequency of the amplifier? (d) What are the values of −VEE and VCC? (e) What are the lower-cutoff frequency and midband gain of the amplifier if RE = 430 kΩ, RC = 220 kΩ, R3 = 510 kΩ, and the Q-point is (15 μA, 5 V) ? (f) What are the values of −VEE and VCC in part (e)?
In the following problems, unless otherwise stated, assume μnCox = 200 μA/V2, μpCOx = 100 μA/V2, λ = 0, and VTH = 0.4 V for NMOS devices and −0.4 V for PMOS devices. If λ ≠ 0, determine the voltage gain of the stages shown in Fig. (1) (a) (b) (c)
Consider a four-input NMOS NOR logic gate with a depletion load similar to the circuit in Figure P16.19. Assume VDD = 2.5 V, VTND = 0.4 V, and VTNL = −0.6 V. The maximum value of vO in its low state is to be 50 mV. (a) Determine KD/KL. (b) The maximum power dissipation in this NOR logic gate is to be 50 μW. Determine the width-to-length ratio of each transistor. (c) Determine vO when (i) two inputs are a logic 1, (ii) three inputs are a logic 1, and (iii) all inputs are a logic 1. Figure P16.19
The transistor parameters for the circuit in Figure P16.21 are: VTN = 0.8 V for all enhancement-mode devices, VTN = −2 V for the depletion-mode devices, and kn' = 60 μA/V2 for all devices. The width-to-length ratios of ML2 and ML3 are 1, and those for MD2, MD3, and MD4 are 8. (a) For vX = 5 V, output vO1 is 0.15 V, and the power dissipation in this inverter is to be no more than 250 μW. Determine (W/L)M L1 and (W/L)M D1. (b) For vX = vY = 0, determine vO2.
Consider the NMOS circuit in Figure P16.22. The transistor parameters are (W/L)X = (W/L)Y = 12, (W/L)L = 1, and VT N = 0.4 V. Neglect the body effect. (a) Determine vO when vX = vY = 2.9 V. (b) What are the values of vGSX , vGSY , vDSX , and vDSY ? [Hint: Set the drain current in each device equal to each other. Also, neglect the terms v2O , v2DSX , and v2DSY ].
Figure P16.23 In the NMOS circuit in Figure P16.23, the transistor parameters are: (W/L)X = (W/L)Y = 4, (W/L)L = 1, VTNX = VTNY = 0.8 V, and VTNL = −1.5 V. (a) Determine vO when vX = vY = 5 V. (b) What are the values of vGSX, vGSY, vDSX, and vDSY? Repeat part (a) for γ = 0.5.
Analog Communication Homework 1 Fourier Transform Consider the following function: g(t) = { −1, 0 < x < 0.5 1, −0.5 < x < 0 0, otherwise a) Find the Fourier transform of g(t) b) Find magnitude spectrum of G(f) c) Find the phase spectrum of G(f) d) Calculate G(f), |G(f)|, phase of G(f) at a frequency of your choice between 1 Hz and 5 Hz, e) Find the frequency where |G(f)| is maximum f) Find the maximum of |G(f)| g) Find the range of frequencies where |G(f)| is above half the maximum