The NMOS transistor in the circuit of Fig. 4 has Vt = 0.5 V, μnCoxW/L = 2 mA/V2, and VA = 30 V. (a) Neglecting the dc current in the feedback network and the effect of ro, find VGS. Then find the dc current IF in the feedback network to verify that you were justified in neglecting the current in the feedback network. (b)Evaluate the gm value using the VGS found in (a). Then, find the small-signal voltage gain, vo/vsig, of this circuit without neglecting the effects of ro and the feedback network. Fig. 4
For an n-channel enhancement-type MOSFET, the threshold voltage is 2 V, the gate voltage is 0 V, the drain voltage is +4 V and the source voltage is −4 V. Which region of operation is the MOSFET in? Select one: a. Cutoff region b. Triode region c. Saturation region d. Forward-active region
a) A MOSFET current source shown in Figure 2 has the following parameters: VTP = −0.4 V, kP′ = 60 μA/V2, (W/L)1 = 25, (W/L)2 = 15, (W/L)3 = 5 Determine the value of resistor R such that transistor M2 is biased at the edge of saturation region (where VSD2 = VSD(SAT)). Figure 2 b) After a design review, a senior design engineer has suggested to increase the output resistance (Ro) by adding ONE additional transistor. Modify the current source in Figure 2 to meet this requirement. Name the circuit, sketch and clearly label all components.
Referring to the figure below, a CMOS gate is shown on the left and the number on each transistor indicates the width of that transistor. We would like to match the worst case delay of the CMOS gate to the inverter delay. Determine the sizes of PMOS and NMOS transistor on the Inverter gate. In the answers, first number shows the PMOS width and the second number shows the NMOS width of the inverter
Consider the MOSFET differential amplifier shown below, with IO = 2 mA, and RL = 10 kΩ, RSS = 100 kΩ, VDD = +8 V and VSS = −8 V. The NMOS transistors in the circuit are nominally identical, with kn = 2 mA/V2, VTnn = 1.0 V and ro = 100 kΩ. The PMOS transistors in the circuit are nominally identical, with kp = 2 mA/V2, |VTp| = 1.0 V and ro = 100 kΩ. a) First consider the DC bias point. Assuming that the current mirror requires at least IV (across Io source) in order to operate, what are the maximum and minimum common-mode DC input voltages (V1 = V2) over which the differential amplifier can operate with both transistors in saturation mode? b) Consider ac small signal operation for differential input (v1 = +Δv/2 and v2 = −Δv/2) and the indicated output (v0 across RL). Find the overall voltage gain (v0/Δv), including sign. c) Find the input resistance and output resistance corresponding to this mode (output resistance is looking to left from capacitor). d) Next, consider ac small signal operation for common-mode input (v1 = v2 = Δv) and the indicated vo. Find the overall voltage gain ((vo/Δv) corresponding to this mode. e) Find the common-mode rejection ratio (CMRR).