Assume VTN = 0.7 V, Kn = 100 μA/V2, VL = 0.2 V Design the NMOS resistive load inverter for operation at a power level of 0.30 mW with VDD = 3.3 V. What is the size of Ms and the value of R? What is the significance of the product K, R in inverter design. Should it be high or low? What are the values for NM and NMI? Find Ron of the NMOS transistor. Verify your design by using this resistance in the voltage division. For an inverter design, what factors determine the values of VL, VDD and power level.
Problem 7.97(a): Design the circuit shown below for a MOSFET having Vt = 0.6 V and kn = 4 mA/V2. Let VDD = VSS = 3 V. Design for a dc bias current of 0.33 mA and for the largest possible voltage gain (and thus the largest possible RD) consistent with allowing a 1.2-V peak-to-peak voltage swing at the drain. Assume that the signal voltage on the source terminal of the FET is zero. For this part, report RS in kΩ. Problem 7.97(b): Design the circuit shown below for a MOSFET having Vt = 0.6 V and kn = 5 mA/V2. Let VDD = VSS = 3 V. Design for a dc bias current of 0.31 mA and for the largest possible voltage gain (and thus the largest possible RD) consistent with allowing a 1.2-V peak-to-peak voltage swing at the drain. Assume that the signal voltage on the source terminal of the FET is zero. For this part, report RD in kΩ.
An NMOS transistor having Vt = 1 V and kn = kn'(W/L) = 1 mA/V2 is operating in the amplifier circuit shown. The DC node voltages at all nodes are indicated on the circuit diagram. Assuming the amplifier is operating linearly in the mid-band frequency range, determine the value of the small-signal Thevenin's equivalent output resistance, Ro = vx/ix (with vsig = 0). a. 667 Ω b. 3 kΩ C. 1.5 kΩ d. 2 kΩ e. 4 kΩ