For the inverter below, μnCox = 360 × 10−6 A/V2, VTN = 0.5 V, μpCox = 150 × 10−6 V/A2, VTP = −0.55 V. Lmin = 180 nm, Wmin = 220 nm, VDD = 1.8 V. Channel length modulation is neglected in the hand calculations but included in the Spice model. a. Assuming (W/L)n = 1 μm/180 nm, find the (W/L)p value that makes VM = VDD/2 = 0.9 V. b. For the (W/L)p value you find in a., find out the VOH, VOL, NMH, NML, VIH, VIL values of the inverter.
Design a CMOS logic gate for the function: Y = (A + B)(CD + E ). Assume that there is only a capacitance CL at the output node. There are no other capacitances at other nodes. a. Draw the circuit schematic for the logic gate. Show inputs clearly and number each transistors (e.g. MN1, MN2, ... for NMOS and MP1, MP2, .. for PMOS) b. Show the paths for worst and best case delays for both tPLH and tPHL. Determine delay times in terms of Req and CL. Give distinct Req values for each transistor (RMN1, RMN2, RMP1, RMP2, etc.). c. Assume there is an inverter designed in the same process as this logic gate that has the size of (W/L)P = k for PMOS and (W/L)N = m for NMOS. In order for the CMOS gate that realizes function Y to have the same tPLH and tPHL as this inverter at the worst case delay scenario, determine the size of each PMOS and NMOS in the gate you designed in terms of k and m respectively.
Consider the inverter chain shown below, with the following assumptions: VDD = 1.0 V CL/C1 = 128 Leff = Lmin = LS = 100 nm Xd = 20 nm Cox = 6 fF/μm2 Co = 0.3 fF/μm Cj = 2 fF/μm2 and please answer the following questions and provide details on your response sheets. What is the sizing factor if N = 6? (Round your final answer to the nearest integer value)
P3 [35 pts] Consider the common-gate amplifier in Figure 3. The MOSFET has KP = 50 uA/V2, W = 600 um, L = 10 um, Vto = 1 V, and λ = 0. The supply voltages are VDD = VSS = 15 V. The resistances are RS = 5 kΩ, RL = 10 kΩ, and RD = 3 kΩ. Determine the operating point (Q) and the value of gm. Derive the expression and value of the input resistance and the voltage gain. Figure 3