P8.10. Consider the NMOS gate shown in Figure 8.39. From the information given, estimate the oxide thickness used in the transistors. Calculate the approximate input capacitance for the inverter. Estimate the maximum fan-out if tP,max = 10 ns. FIGURE 8.39 NMOS gate (P8.10).
In the circuit of figure below, assume that ISS = 1 mA and W/L = 50/0.5 for all the transistors. (a) Determine the voltage gain. (b) Calculate Vb such that ID5 = ID6 = 0.8(ISS/2). (c) If ISS requires a minimum voltage of 0.4 V, what is the maximum differential output swing? VDD = 3 V, μnCox = 134 μA/V2, Vthn = 0.7 V, λn = 0.1 V−1 for L = 0.5 μm μpCox = 38.3 μA/V2, |Vthp| = 0.8 V, λp = 0.2 V−1 for L = 0.5 μm
10a) (15 Points) In the following circuit, an NMOS transistor is used to switch the current to the LED. Assume the following parameters: Microcontroller: vO = 4.6 V iOH < −5 mA and vOL = 0.4 V, iOL < 8 mA LED: vf = 2.0 V, PLED−max = 200 mW Desired LED current 100 mA Transistor: vT = 1.0 V, RDS(ON) = 0.5 Ω, iD−max = 500 mA a. When the output of the microcontroller is low, what is the operating region of the transistor? b. When the output of the microcontroller is high, what is the operating region of the transistor? c. With the microcontroller output high, and the transistor in the ohmic region, what value of R results in an on-state LED current of 100 mA? d. What standard value of resistor (Table is on page 33 of the text) comes closest to the desired LED current? 10b) Suppose we rearrange the NMOS circuit in problem 10 as shown. Using the same parameters as in the previous problem, answer the following: a. When the output of the microcontroller is low, what is the operating region of the transistor? b. Suppose that when the output of the microcontroller is high, there is 100 mA current through the LED with the same resistor as found in problem 10a. What is the source voltage relative to ground? What is the gate-source voltage? c. Do you expect this arrangement to work for controlling the LED? Explain. 10c) (15 Points) In this problem, the NMOS transistor in problem 10b has been replaced with a PMOS transistor as shown. Assume all the parameters are the same, noting that the gate must be the threshold voltage below the source to get out of cutoff. a. When the output of the microcontroller is high, what is the operating region of the transistor? b. When the output is low, what is the operating region of the transistor? c. Does this arrangement to work for controlling the LED? Explain.
Consider the following circuit where R1 = 17 Ω, β = 85. Assume ICQ = 3.5 mA and VT = 25 mV. VCC and VB are constant. Neglect the Early effect. Find the input resistance Rin in ohms
For the circuit shown, find the collector resistance RC that will keep this npn transistor in active mode. VBE = 0.7 V. β ranges between 100 and 200. Note that the active mode operation for this BJT requires VCB ≥ −0.4 V. IB = 5 μA. Vcc = 6 V. Pick the Rc value that will put the transistor in deep saturation.
For the MOSFET differential pair amplifier circuit shown below, ISS = 50 μA, RSS = 100 kΩ, μnCox = 500 μA/V2, μpCox = 100 μA/V2, λn = 0.05 V−1, λp = 0.05 V−1, (W/L)n = 10/2, and (W/L)p = 50/2: a) Determine the small-signal differential mode gain of the circuit, Av,DM. (5 points). b) Determine the small-signal common mode gain of the circuit, Av,CM. (5 points). c) Determine the small-signal common-mode to differential-mode conversion gain of the circuit, ACM−DM, if transistor M2 is mismatched such that (W/L)2 = 10/1.9. (10 points) d) Determine the common-mode rejection ratio of the circuit, CMRR. (5 points)
The NMOS transistors in the circuit have VTN = 0.5 V, μnCox = 250 μA/V2, L1 = L2 = 0.25 μm, and λ = 0. Let us do some calculations here. Find the required values of gate width for each of Q1 and Q2, and the value of R to obtain the voltage and current values indicated.
(P5.11) A p-channel MOSFET with a threshold voltage of Vtp = −0.7 V has its source connected to ground. i. What should the gate voltage be for the device to operate with and overdrive voltage of |VOV| = 0.4 V? ii. With the gate voltage as in (i), what is the highest voltage allowed at the drain while the device operates in the saturation region? iii. If the drain current obtained in (ii) is 0.5 mA, what would the current be for VD = −20 mV and VD = −2 V? Answers: 5.11 (a) −1.1 V; (b) −0.4 V; (c) 0.05 mA; 0.5 mA
(1 point) The transistor in Fig. 1 is operating with Vov = 0.65 V. Consider kn = 350 μA/V2, VDD = 3 V, Vtn = 0.7 V and RD = 3.5 kΩ. Design RS for saturation mode operation and verify the operating condition.
Consider a CMOS inverter utilizing the devices with parameters for NMOS: μnCox = 250 × 10−6 A/V2, VTN = 0.8 V, λN = 0.01, (W/L)n = 5 μm/ 500 nm μpCox = 120 × 10−6 V/A2, VTP = −0.9 V⋅ λP = 0.015, (W/L)p = 5.5 μm/500 nm, VDD = 5 V. a. Find the VM value for the inverter. Include the channel length modulation effect. You can use MATLAB or a similar tool to solve the equation, but show how you build the equation. b. Keeping the NMOS size constant, find the proper size that results in tPHL = tPLH.
P5. [DC bias and swing] A n -channel MOSFET with kn = 10 mA/V2, threshold voltage Vtn = 1 V, VDD = 4 V, RD = 1 kΩ, λ = 0. (1) Draw VTC: VDS vs. VGS; (2) Denote region transition coordinates on the VTC curve (A: cut-off -> saturation, B: saturation -> triode, C: gate voltage = VDD); (3) If the biasing VGS|Q = 1.5 V, please determine the biasing current IDS, DC drain-source voltage VDS∣Q and signal voltage gain Av = vds/vgs around this biasing point Q. (4) Please determine the allowable symmetric input signal swing peak vgs,peak that maintains the operations within saturation region with the help of the VTC. (5) Assuming that you do not have VTC, estimate the vgs,peak again by assuming constant voltage gain around Q (hint: saturation region: VDS−vds >= VGS + vgs)
P4. [Vgs vs. Id] A n-channel MOSFET with kn = 10 mA/V2, threshold voltage Vtn = 1 V, find VGS and VDS when the transistor is working at the boundary of saturation-triode across various drain current ID.
In the following circuit, the high and low DC voltage sources are: VDD = 5 V and VSS = −5 V respectively. Consider that all three external capacitors have high values. The PMOS transistor has a threshold voltage Vt = −1 V and kp′(W/L) = kp = 0.4 mA/V2, and the NMOS transistor has a threshold voltage equal to Vt = 1 V and kn′(W/L) = 2 mA/V2. a) Determine the DC drain voltage of the PMOS transistor. b) Determine the DC source voltage of the NMOS transistor
The plot shows the drain current vs. drain voltage for a MOSFET with VT = 2 V and VGS = 4 V. a. Determine the Early voltage VA. b. Determine λ. Answer check: ∼0.022 c. Determine the output resistance RO. Answer check: 1875 ohms d. Estimate the value of k for this MOSFET (Hint: Assume saturation, and use the extrapolated current at VDS = 0). Answer check: 12 mA/V2 e. What would be the drain current at VGS = 3 V and VDS = 20 V? Be sure to include the effect of channel length modulation. Answer check: 8.6 mA
Design a complex CMOS gate implementation of the following function: Y = A⋅(B + C)⋅D¯ a) Draw a logic circuit schematic for Y in which the Pull-Up Network (PUN) is the dual of the Pull-Down Network (PDN). Make sure to draw any necessary inverters for inputs. b) Assume that a basic matched inverter has a channel length of L = 0.25 μm, an NMOS channel width of WN = 0.5 μm and a PMOS channel width of WP = 1.0 μm, and that this sizing guarantees at least equal output current driving capability (i.e., equal high-to-low and low-to-high propagation delays). Determine the proper W/L ratios for each transistor in the complex logic gate to ensure a current driving capability at least equal to that of the basic matched inverter. Keep the W/L ratios as small as possible to minimize the gate's area. Calculate the total area of the complex CMOS circuit, including the area of the inverters for inputs.
For this problem, neglect capacitances and ro in transistors and use long-channel equations. M1 is operated with Vov = 0.6 V. The amplifier is intended to be used with a source resistance RS = 50 Ω. (a) Calculate (W/L)1 for an input impedance equal to 50 Ω. What is the required ID1? (b) If (W/L)2 = (W/L)3 what is the required value if I bias ? (c) Calculate R for a voltage gain vo/vi = 10 (d) Symbolically, calculate the NF considering the contribution of M1, M2 and R. (e) To reduce noise figure, is it better to use a high or a low overdrive in M2 and M3? Explain why. (f) If |Vov2| = 1 V, calculate (W/L)2, the DC component at vo and F in dB. CMOS process data: VDD = 1.8 V. For NMOS, Vthn = 0.4 V, μn = 400 cm2/Vs, Cox = 9 fF/μm2 and γn = 1. The parameters for PMOS transistors are k′ = μpCox = 90 μA/V2, Vthp = −0.4 V and γp = 0.8.