A die draws a transient current of 1 A in time 2 ns from a voltage source (battery) at voltage Vdd through the package causing an AC offset of 50 mV to the transistor power supply Vdd. Calculate the inductance of the package. Note: 1 nH = 10 −9 H 0.5 nH 1 nH 2 nH 0.1 nH
What are the voltage levels at nodes W, X, Y and Z in the circuit below in the steady state, assuming that input A goes from VD to 0 whereas inputs B through E go from 0 to VDD? The threshold voltage of NMOS transistors is VT. Hint: You may ignore the body bias effect.
Consider the following 2T DRAM design. All NMOS transistors are minimum sized ones with W/L ratio of 2:1. The drain diffusion capacitance and gate capacitance of the two transistors are Cd = 15 fF and Cg = 25 fF, respectively. Given k′ = μnCox = 100 μA V2, Vt,n = 0.3 V, CRBL = CWBL = 400 fF, VDD = 1.5 V, γ = 0.15 V, 2φF = −0.6 V and when accessed WL = VDD and RL¯ = 0 V. a) What is the effective store-node capacitance value, Cs? Hint: There is no explicit capacitance present at the storage node. b) Consider writing a '1' to this cell, what is the maximum voltage that can be observed at this storage node? Hint: To write a '1', WBL is driven high (its voltage goes to VDD). c) During a subsequent read operation, what should be the minimum pulse width of RLBAR for a voltage drop of VDD − 2Vtn2 on RBL? Hint: During the read, RBL is pre-charged to VDD before the cell is accessed.
Construct a small signal model including all the capacitance from M1 and M2. Identify the capacitors that can be ignored and simplify the model. 10pt Identify the Miller capacitor and construct a new small signal model by applying Miller theorem. 10pt Find the transfer function Vout(s)/Vin(s). 10pt Find the magnitude response expression under the sinusoidal steady state condition. 5pt Find the phase response expression under the sinusoidal steady state condition. 5pt Construct a magnitude Bode plot. 5pt Construct a phase Bode plot. 5pt
For the circuit shown below, transistors T1 and T2 are the same with VT = 0.6 V and k = 5 mA/V2. Find the value of R2 that will result in T2 operating at the edge of saturation. VG1 = VG2 = VD1 = 0.8 V Keeping T2 at the edge of saturation: VD2 = VG2 − VT = 0.8 − 0.6 = 0.2 V I D 2 = k/2(VG2 − VT) 2 = 0.1 mA Hotseat: Determine R2. A. 6 kΩ C. 12 kΩ B. 20 kΩ D. 26 kΩ
In Figure 5, RI = 200 Ω, RS = 70 kΩ, RL = 200 kΩ, RD = 50 kΩ and VDD = VSS = 15 V. Kp = 200 μA/V2, VTP = −1 V and λ = 0.02 V−1. Calculate the Q-point of this amplifier VSD = V, ID = mA. Figure 5. VSD = V ID = mA
The circuit in Figure 1 is a level shift circuit. It achieves a DC level shift between the input and the output. The value of this shift is determined by the current I0. Assume Xd = 0, y = 0.4, 2|φf| = 0.6 V, VT0 = 0.43 V, kn = 115 μA/V2 and λ = 0. a. Suppose we want the nominal level shift between Vi and Vo to be 0.6 V in the circuit in Figure 1-a. Neglecting the body effect, calculate the width of M2 to provide this level shift (Hint: first relate Vi to Vo in terms of Io). b. Now assume that an ideal current source replaces M2 (Figure 1-b). The NMOS transistor M1 experiences a shift in VT due to the body effect. Find VT as a function of V0 for V0 ranging from 0 to 2.5 V with 0.5 V intervals. Plot VT Vs. Vo c. Plot Vo vs. Vi as Vo varies from 0 to 2.5 V with 0.5 V intervals. Plot two curves: one neglecting the body effect and one accounting for it. How does the body effect influence the operation of the level converter? d. At Vo (with body effect) = 2.5 V , find Vo (ideal) and thus determine the maximum error introduced by the body effect. (a) (b) Figure 1 - NMOS Level Shifter
The NMOS amplifier below is to be designed to provide a 0.2 V peak output signal. Assume VDD = 1.8V, RD = 10kΩ. (4 points each part) a) If the gain is to be −10 V/V, what gm is required? b) Bias the amplifier as close to the edge of the saturation region as possible consistent with the required signal swing. Specify the required values of VOV and ID. c) If kn′ = 380 μA/V2, what W/L ratio is required? d) If Vt = 0.4 V, find VGS. D 7.26 The NMOS amplifier of Fig. 7.10 is to be designed to provide a 0.2−V peak output signal. Assume VDD = 1.8 V and RD = 10 kΩ. If the gain is to be −10 V/V, what gm is required? Bias the amplifier as close to the edge of the saturation region as possible consistent with the required signal swing. Specify the required values of VOV and ID. If kn′ = 380 μA/V2 what W/L ratio is required? If Vt = 0.4 V, find VGS.