In the following circuit, assume that λ = γ = 0, VDD = 3 V, |VTH| = 0.5 V, μPCox = 20 μA/V2. Furthermore, assume that vin is a small signal source and Vbias1 = 1.5 V and the DC level of Vout1 and Vout2 are all equal to 0.5 V and 1.5 V, respectively. Also, assume that the bias current of M1 is twice that of M2. (Hint: ID = 1/2μpCOX(W/L) (|VGS| − |VTH|)^2, in saturation) (1) What is the region of operation of M1 and M2? (10 points) (2) If the overall power consumption is 3 mW, find R1, R2, (W/L)1, (W/L)2. (15 points) (3) What is the small signal gain of the circuit (vout2/vin)? Assume there is no parasitic effect and gm1 = gm2 = 4/3 mV/V. (15points)
Half-Circuit Find the differential half-circuit for the differential amplifier shown in Fig. 2 and use it to derive an expression for the differential gain Ad = vo/vid in terms of gm, RD, and RS. Neglect the Early effect. What is the gain with Rs = 0? What is the value of Rs in terms of 1/gm that reduces the gain to half this value? Fig. 2
Dynamic CMOS Circuits (a) During precharge (Clk=0), All inputs are logic 0 for the following Dynamic 3NAND. During evaluation (Clk=1), A is activated (0 → 1). Given VDD = 1.5 V, Vtn = 0.5 V, CL = 150 fF, C1 = 25 fF, and C2 = 50 fF, what is the final output voltage? (b) Calculate C1 of the following circuit so that the final voltage is determined by A input. CL = 175 fF, VDD = 1.5 V, and Vtn = 0.5 V. Assume that all inputs are logic 0 during the precharge. (c) i) Write the Boolean expression for OUT of the following circuit. ii) VDD = 2.0 V and Vtn = 0.5 V. During precharge (Clk = 0), All inputs are logic 0. During evaluation (C∣k = 1), A and B are activated (0 → 1). What is the final voltage when the evaluation mode settles?
For the given Fig., for VDD = 5V, and threshold voltage (VTH) of NMOS transistors M1, M2, M3 = 1 V. The value of Vmax3 is 5 V 4 V 3 V 2 V
6.7 One Ids − Vds curve of an ideal MOSFET is shown in Fig. 6-43. Note that Idsat = 10 −3 A and Vdsat = 2 V for the given characteristic. (You may or may not need the following information: m = 1, L = 0.5 μm, W = 2.5 μm, TOX = 10 nm. Do not consider velocity saturation.) (a) Given a Vt of 0.5 V, what is the gate voltage Vgs one must apply to obtain the I−V curve? (b) What is the inversion-layer charge per unit area at the drain end of the channel when the MOSFET is biased at point (1) on the curve? (c) Suppose the gate voltage is changed such that Vgs−Vt = 3 V. For the new condition, determine Ids at Vds = 4 V. (d) If Vd = Vs = Vb = 0 V, sketch the general shape of the gate capacitance C vs. Vg to be expected from the MOSFET, when measured at 1 MHz. Do not calculate any capacitance but do label the Vg = Vt point in the C−V curve.
a. In the given circuit, the MOSFET operates based on the model iD = K(vGS − Vt)^2, as long as vds ≥ vGS−VT, where K is 1.16 milli-siemens per volt, and VT = 0.6 volts. The resistances R1 and R2 are 590 kilo-ohms and 100 kilo-ohms, respectively. What is the maximum value of RD for which the device is in saturation? Provide your answer in kilo-ohms. b. In the given circuit, assuming RD = 4 5 kilo-ohms, what is the maximum current iD that can flow through the device while ensuring the device remains in saturation? For this question, disregard the earlier values of R1 and R2.