Consider the CMOS common source amplifier circuit in Fig. 4. The transistor parameters are given as VTN = 0.5 V, VTP = −0.5 V, kn′ = 80 μA/V2, kp′ = 40 μA/V2, and λn = λp = 0.015 V −1. Assume that IBias = 0.1 mA and M2, M3 are identical. (a) Determine the small-signal parameters (gm and ro) of each transistor. (Express the transconductance gm in terms of the width-to-length ratio (W/L) without any values). (b) Draw the small-signal equivalent circuit and derive the small-signal voltage gain equation. (c) Find the width-to-length ratio of M1 such that the small-signal voltage gain is Av = −250. (d) Derive and calculate the output resistance Ro. Figure 4. CMOS common source amplifier circuit for the Question 4
D 8.44 Consider the CMOS amplifier of Fig. 8.16(a) when fabricated with a process for which kn′ = 4kp′ = 400 μA/V2, |Vt| = 0.5 V, and |VA| = 5 V. Find IREF and (W/L)1 to obtain a voltage gain of −40 V/V and an output resistance of 100 kΩ. Recall that Q2 and Q3 are matched. If Q2 and Q3 are to be operated at the same overdrive voltage as Q1, what must their W/L ratios be?
Consider the CMOS common-source amplifier in Fig. 7.4(a) for the case VDD = 3 V, Vtn = |Vtp| = 0.6 V, μnCox = 200 μA/V2, and μpCox = 65 μA/V2. For all transistors, L = 0.4 μm and W = 4 μm. Also, VAn = 20 V, |VAp| = 10 V, and IREF = 100 μA. Find the small-signal voltage gain. Also, find the coordinates of the extremities of the amplifier region of the transfer characteristic-that is, points A and B. (a)
Problem 3: Using graphical methods, find the output voltage of the enhancement-mode MOSFET follower if (1) VIN = 10 V; (2) VIN = 2 V. The MOSFET has parameters K = 0.5 mA/V2 and VTR = 2 V. The Thevenin circuit has values VDD = 15 V and Rs = 1 kΩ.
For a CMOS inverter fabricated in a 65nm process with VDD = 1.0 V, Vtn = Vtp = 0.35 V, K′n = K′p = 500 A/V2, and having (W/L)n and (W/L)p = 4. Find TPHL, TPLH, and TP, when the equivalent load capacitance C = 4 fF. Use the method of average currents. Now, create a NAND gate with worst-case pull-up and pull-down that match the current drive of the inverter. Calculate the worst and best case delays with equivalent load capacitance C = 4 fF. Use the method of average currents.
A defective CMOS inverter has a resistor R with resistance 14.6 kΩ shorting the NMOS transistor as shown in the circuit below. The supply voltage is 5 V, and the transistor parameters are the following: kn = kp = 0.1 mA/V2, VTN = −VTP = 1 V. 5. Find the value of the output voltage in V when the input is 0 V. a) 4.3 b) 4.2 c) 4.5 d) 4.4 e) 4.6 6. Find the value of VOL in V . a) 0.10 b) 0 c) 0.20 d) 0.30 e) 0.40
Consider the circuit above. This circuit is a common gate amplifier. Assume the NMOS M1 is in saturation. The ideal current source I = 0.5mA. For M1, kn = 0.25 mA/V2, and λ = 0. C1 and C3 have infinite capacitance. RS = 1kΩ, RG = 100kΩ, RD = 10kΩ, RL = 50kΩ. (a) What is the input impedance Rin, indicated by the arrow? (b) What is the total voltage gain: Av = vo/vs?
(1) Identify the type of single stage amplifier for each of the amplifiers below (CS, CD, or CG). (2) Find the small signal input resistance, Rin, output resistance, Rout, transconductance gain, Gm, voltage gain, Av, of the following amplifiers. The answers should be in terms of gmi, gmbsi, and goi (roi), where i = 1 , 2 , 3 , or 4 . Consider bulk and channel modulation effects.
The NMOS transistor in Figure 3 has VTH = 0.8 V, λ = 0, and μnCox = 50 μA/V2. The input voltage Vi takes values between 0 V and 3 V. a. When Vi = VDD, the output voltage is 0.25 V. What is the W/L ratio of the transistor? b. Find the value at which the output voltage is equal to the input voltage (Vi = Vo = VM). Figure 3 for Q3
A bandgap voltage reference is shown in Figure 2, where R2A = R3A and R2B = R3B. The size ratios of M1:M2:M3 = 1:1:1. The emitter area ratio of Q1:Q2 = N:1. All resistors are made by the same materials. The opamp is ideal. Neglect channel-modulation effect, find the expression of VREF. Figure 2
Given that kn′ = 100 uA/V2 and Vt = 0.6V, find VH and VL for the NMOS logic inverter with resistor load shown in Figure 5. Note that VH and VL are the output values (vo) corresponding to the input values (vI) of low and high respectively. What is the power dissipation for the inverter? Note that VDD = 2.5 V, R = 400 kΩ, and W/L = 3/1 (12 points) Figure 5
a. For the circuit shown below, show a clean and labeled small signal equivalent circuit and derive the expression for vo/vb, (vb is the small signal voltage at the base node) vo/vsig, Rin and Rout. (b) This is the design part. The specifications are as follows: The required gain vo/vb = −120 V/V, Ic = 1 mA. and the require voltage swing at the output is ±3 V around the DC value of the output. (Hint: Do not use the generic design rule. You should be able to find the DC voltages at the collector and emitter from the specifications). Assume Vcc = 8 V. For this design assume VA = ∞ (this makes ro = ∞), V T (Thermal Voltage) = 25 mV, VBE = 0.7 V, VCEsat = 0.3 V and β = ∞. Find the values of RC, RE, RB1, and RB2. (c) If the β = 100 instead of the design value, find the new Ic. Now assuming VA = 50 V find vo/vsig, Rout and RIN. For this part assume Rsig = 10 kΩ. Punt: If you could not answer (b), use RC = 3 kΩ, RE = 2 kΩ, RB1 = 50 kΩ, and RG2 = 30 kΩ (d) Run a transient simulation of the designed circuit in Multisim. Use the same BJT used in the lab simulation. Show the input voltage v sig and output voltage v o on the same plot. Choose vsig to be at 1 kHz and 10 mV peak sinusoidal. Compare with calculated value of the gain in part c.