Problem 1 For the 2 circuits shown circuits, RD = 0.75 kΩ, RS = 0.5 kΩ, VDD = 14 V, VSS = 14 V, λ = 0.05 V−1, K = 0.4 mA/V2, Vtn = 1 V, |Vtp| = 1 V For the circuit on the Left (n-channel), VDS = 5 V: Write 2 KVL equations and find ID, vOV and, VT, and state FET region of operation. 2. For the circuit on the Right (p-channel), VSD = 5 V: Write 2 KVL equations and find ID , vOV and, VT, and state FET region of operation.
(a) A non-ideal Op-Amp configured with resistors is shown in Figure 1(a). The OpAmp is powered by ± VDD power supplies with VDD = 15 V. It has two AC input sources, v1 and v2, 2 non-ideal DC current sources, I+ and I−, and a non-ideal DC voltage source VIO. Derive the expression for the output voltage vout, in terms of all or some of the followings: v1, v2, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, I+, I− and V10. Note: Parallel resistance of Ra and Rb can be written as Ra//Rb without expanding it. Figure 1(a)
(a) What is the logic function implemented by the pass transistor logic shown in figure. (b) Calculate the minimum and maximum propagation delay. All transistors have minimum length, L = 0.25 μm. Use Cg = 2 fF/μm, Cd = 1 fF/μm and W = 0.5 μm. Assume that the equivalent resistance of NMOS transistor of width W is 13kΩ; the equivalent resistance of PMOS transistor of width 2W is 13kΩ; the equivalent resistance of transmission gate with width of both NMOS and PMOS transistor W) is 13kΩ.
Shown is a dynamic domino logic gate. While the CLK is Vdd input A changes value from 0 to Vdd. What will be the output of the logic gate? Is the value correct (proper value of the output is 0)? Use the following parameters: Cg = 2 fF/μm, Cd = 1 fF/μm; kn′ = 115 μA/V2, kp′ = 30μA/V2, Vtn = 0.4 V, Vtp = −0.4 V, VDD = 2.5 V, λn = λp = 0 V−1; W = L = 2λ = 0.25 μm.
Calculate the propagation delay from the falling edge of the clock to the output. Use the following values: W = 2λ = 0.25 μm, L = 2λ = 0.25 μm, Cg = 2 fF/μm, Cd = 1 fF/μm and R = 13 kΩ (NMOS transistor with width W and PMOS transistor with width 2W ).
Shown is a positive latch built using transmission gates. Calculate the setup time, tsetup , and the propagation delay from the input D to the output Q, td−q. Use Cg = 2 fF/μm, Cd = 1 fF/μm and W = L = 2λ = 0.25 μm. Assume that equivalent resistance of NMOS transistor of width W is 13 kΩ and that equivalent resistance of PMOS transistor of width 2W is 13 kΩ, that is use the following values for the transistor resistances: Rsq,n = 13 kΩ and Rsq,p = 26 kΩ.
A minimum-size inverter is fabricated in a 0.25μm technology to has (W/L)p = (W/L)n = 0.25/0.25, Vtn = −Vtp = 0.5 V, μnCox = 267 μA/V2, μpCox = 93 μA/V2. The supply voltage VDD = 2.5V. In a procedure to determine VIL: Are Qn and Qp matched? Given the Q's data above and by equating the currents flowing in Qn and Qp at VIL: a) Derive equation (1) in two variables Vin and Vout. b) Differentiate equation (1) with respect to Vin and put dVout/dVin = −1 to get equation (2) in Vin and Vout. Eliminate Vout between equations in (1) and in (2) to get a value for Vin = VIL. Determine the low noise margin NML. Derive the expression for the inverter threshold VM and determine its value using the same parameters above. Comment on the symmetry of the inverter VTC (Voltage Transfer Characteristics) around VDD/2.
Consider the following amplifier operating at 300 K. The transistor M1 has μnCox = 250 μA/V2 and Vth = 0.4V. You may assume that M1 operates in saturation region and neglect its channel length modulation (λ = 0). The supply voltage VDD is 1.8V. (a) Find the expression for the input resistance (Rin) assuming that M1 has the transconductance of gm in saturation region. (b) Find the expression for the voltage gain AV=Vout /vin. (c) Explain the phase relationship between the vin and Vout signals. In other words, are they in phase or out of phase? Explain the reason why. (d) If this amplifier stage must provide an output resistance of 500 Ω, what is the maximum allowable value for ID of M1 that keeps M1 in saturation? (e) For the ID value obtained from (d), calculate the required value of W/L that makes the voltage gain Av equal to 10. (f) Calculate the maximum load capacitance (Cout ) that the amplifier can drive at its output while keeping its −3dB bandwidth above 100 MHz.
Consider the following ID−VG characteristics shown for two transistors of equal size, one with a higher threshold voltage (VTH) and another with a lower threshold voltage (VTL) (note: ID axis is in log scale). Assume that VTH is 100mV higher than VTL = 100 mV. a. If the low VT transistor shows an OFF current of IOFFL = 1 nA at room temperature (27∘C), estimate the OFF current of the high VT transistor (IOFFH) at room temperature. b. Estimate the OFF current of both transistors at 100∘C and compare the values with the values at room temperature. c. If the high VT transistor operates at supply voltage VDDH = 1 V and the low VT transistor operates at supply voltage VDDL = 0.5 V, estimate the standby power consumption of a chip that contains one billion of high VT off transistors operating at VDDH = 1 V and the standby power of a chip that contains one billion of low VT off transistors operating at VDDL = 0.5 V. Perform the power estimation for room temperature and 100∘C. d. Compare the standby power consumption of the low VT chip with the high VT chip and explain the difference.
A full wave rectifier with a smoothing capacitor and the output waveforms are shown below. If the frequency of the AC signal f = 50 Hz, and the diode
A full wave rectifier with a smoothing capacitor and the output waveforms are shown below. If the frequency of the AC signal f = 50 Hz, and the diode conduction angle ΘCOND = 35 degrees, what is the capacitor discharge time Δt? (Enter your answer in ms)