Design the transistor inverter of Fig. 11-4 to operate with a saturation current of 8 mA using a transistor with a beta of 100. Use a level of IB equal to 120% of IB(max) and standard resistor values.
Consider a mixer is shown in the figure 3. gm2 = 50 mS, RD = 2 kΩ, Assume that the transistors are long channel devices with λ = 0. Also, assume M2 does not enter the triode region. Assume abrupt edges and a 50% duty cycle for the L0 and neglect channel. length modulation and body effect. Assume that M1 is an ideal switch. If we decide to replace the RD by inductor L1 = 1 nH with a quality factor of 20 at 1 GHz. the voltage conversion gain of the circuit becomes
For the following transfer characteristic for an nMOS MOSFET at VDS = 0.5V so you can safely assume that you are in triode region above threshold: a. Write down the threshold voltage (5) VGS = 1.5v b. Given that the channel electron mobility μn = 1200 cm2/Vs, and that the oxide thickness is 20 nm, determine the W/L ratio (20).
Problem III : Single Stage amplifier with resistive feedback bias Figure 5 Figure 5 uses resistive feedback to make an amplifier using a CMOS inverter. (a) Use the procedure discussed in Tutorial 2 to find the value of Rx to make this circuit work as an amplifier. (b) LTSpice: Implement the circuit in LTSpice using the models for NMOS and PMOS transistors provided to you. Compare the gain obtained via simulation to your earlier estimate of gain. Ensure that vin has a small enough amplitude that the amplifier does not distort the output. (c) LTSpice : Perform an AC analysis to obtain the magnitude and phase response of this amplifier.
Problem 3 (6 points) Consider the NMOS characteristics next where the three drain current curves are at VGS equal to 3 V, 2.5 V, and 2 V, respectively. Estimate transconductance gm and drain resistance rd, assuming the VGSQ = 2.5 V (the middle curve), VDSQ = 5 V, and IDSQ = 7.39 mA.
Design the presented circuit, calculating the appropriate values for RD and RS to ensure the transistor functions with a drain current (ID) of 0.4 mA and a drain voltage (VD) of +0.5 V. Consider an NMOS transistor characterized by a threshold voltage (Vt) of 0.7 V, a mobility-capacitance product (μnCox) of 100 μA/V2, a channel length (L) of 1 μm, and a width (W) of 32 μm. Ignore the channel-length modulation effect by assuming λ = 0.
Q.2(a) An NMOS transistor, operating in the linear region with VDS = 50 mV, is found to conduct 25 μA for VGS = 1 V and 50 μA for VGS = 1.5 V. What is the apparent value of threshold voltage VT? If kn′ = 50 μA/V2, what is the device W/L ratio? What current would you expect to flow with VOS = 2 V and VDS = 0.1 V ? If the device is operated at VGS = 2 V, at what value of VDS will the drain end of the MOSFET channel just reach pinch-off? [4][CO1] (b) Design a CMOS inverter with switching threshold voltage of 2/3VDD. What is the resulting ratio of WP/WN ? (Assume LP = LN, μN = 2.5μP, |VTP| = VTN = 0.2VDD, [4][CO2]
Add intrinsic capacitors to the transistor M1, M2, M3. 10pt Identify capacitors that can be ignored and simplify the circuit. 10 pt Construct a small signal model to find Vout/Vin. λ1 = 0, λ2 ≠ 0, λ3 ≠ 0. 10pt Find the transfer function Vout(s)/Vin(s) and identify the poles and zeros. 10 pt Find the input impedance. 5 pt Find the output impedance. 5 pt
(a) Figure Q2(a) shows a differential amplifier with a current source at the bottom. It is given that VDD = VSS = 15 V, ISS = 300 μA, Early effect can be ignored (λ = 0), Kn = 400 μA/V2 and VTN = 1 V. You may assume MOSFET in saturation region. (i) For single ended outputs, draw the half-circuits and derive the algebraic equations for the differential mode and common-mode gains as well as CMRR. [6 Marks] (ii) For the above case of single ended output, what should be the value of Rss to get CMRR = 100? [4 Marks] Figure Q2(a) (b) Figure Q2(b) shows a MOSFET based current mirror. Draw the AC small signal model and derive an equation for output resistance Rout as shown in the figure. You can keep your answer in terms of gm, ro etc but denote the subscript 1,2,3 etc to indicate which transistor. In other words, denote transconductance of M2 by writing gm2 and so on. [6 marks] (c) Draw the diagram of a BJT based Class B push-pull power amplifier and derive the maximum possible power efficiency of this circuit. You may ignore crossover distortion and assume |VCE(sat)| = 0 V. [9 marks]
In the above circuit, the NMOS transistors have Kn = 20 mA/V2 and the PMOS transistors have Kp = 5 mA/V2. a) For the given differential inputs, determine the direction of the small signal currents at the source of each NMOS, at the drain of each NMOS, at the source of each PMOS and at the drain of each NMOS. b) For differential inputs, determine the transconductance short circuit gain (iout = isc) AG = isc/VDM. c) Based on your part a and b answers, for differential inputs, determine the transconductance short circuit gain (iout = isc) AG = isc/VDM.
Q5. An amplifier is to be constructed using a n-channel enhancement type MOSFET which has a conduction parameter of k = 50 mA/V2 and a threshold voltage VTH = 1.8 V. Given that RD = 420 Ω, determine the answers for the following questions (20 marks) Figure Q5 a) Design the values of the resistors, R1, R2 and RS, required to bias the MOSFET amplifier at VG = 5 V and drain current at ID = 16 mA. (6 marks) b) Compute the values of VGS and VDS. (6 marks) c) Sketch the transfer curve and DC load line of the circuit and define the Q-point, VTH, VGSO, ID(max) and IDQ points on the graph. (8 marks)